CM0的启动引导区设置（RM0091）

The values on both BOOT0 pin and nBOOT1 bit are latched on the 4th rising edge of 
SYSCLK after a reset. It is up to the user to set nBOOT1 and BOOT0 to select the required 
boot mode.
The BOOT0 pin and nBOOT1 bit are also re-sampled when exiting from Standby mode. 
Consequently they must be kept in the required Boot mode configuration in Standby mode. 
After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 
0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.
Depending on the selected boot mode, main Flash memory, system memory or SRAM is 
accessible as follows:
● Boot from main Flash memory: the main Flash memory is aliased in the boot memory 
space (0x0000 0000), but still accessible from its original memory space 
(0x0800 0000). In other words, the Flash memory contents can be accessed starting 
from address 0x0000 0000 or 0x0800 0000.
● Boot from system memory: the system memory is aliased in the boot memory space 
(0x0000 0000), but still accessible from its original memory space (0x1FFF EC00).
● Boot from the embedded SRAM: the SRAM is aliased in the boot memory space 
(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).
Physical remap
Once the boot pins are selected, the application software can modify the memory 
accessible in the code area. This modification is performed by programming the 
MEM_MODE bits in the SYSCFG configuration register 1 (SYSCFG_CFGR1). Unlike 
Cortex M3 and M4, the M0 CPU don't support the vector table relocation. For application 
code which is located in a different address than 0x0800 0000, some additional code must 
be added in order to be able to serve the application interrupts. A solution will be to relocate 
by software the vector table to the internal SRAM: 
● Copy the vector table from the Flash (mapped at the base of the application load 
address) to the base address of the SRAM at 0x20000000. 
● Remap SRAM at address 0x00000000, using SYSCFG configuration register 1.
● Then once an interrupt occurs, the CortexM0 processor will fetch the interrupt handler 
start address from the relocated vector table in SRAM, then it will jump to execute the 
interrupt handler located in the Flash. 
This operation should be done at the initialization phase of the application. Please refer to 
AN4065 and attached IAP code from www.st.com for more details. 
Embedded boot loader
The embedded boot loader is located in the System memory, programmed by ST during 
production. It is used to reprogram the Flash memory using one of the following serial 

interfaces: USART1(PA9/PA10) or USART2(PA14/PA15).

   对于BOOT1的写入可以借助STLink或者在程序中使用Flash的库函数进行写入。