HDLBits刷题之Circuits-＞Combinational Logic-＞Multiplexers

目录

Mux2to1

Write your solution here

Mux2to1v

Write your solution here

Mux9to1v

Write your solution here

Mux256to1

Write your solution here

Mux256to1v

Write your solution here

---

Mux2to1

Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

Write your solution here

module top_module( 
    input a, b, sel,
    output out ); 
    //always @(*) begin
    //    if(sel)
    //        out=b;
    //   else
    //        out=a;             
    //end
    assign out = sel?b:a;
    
endmodule

Mux2to1v

Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

Write your solution here

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );

    assign out =sel?b:a;
        
endmodule

Mux9to1v

Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

Expected solution length: Around 15 lines.

Write your solution here

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    
    always @(*) begin
        case(sel)
            4'd0:out=a;
            4'd1:out=b;
            4'd2:out=c;
            4'd3:out=d;
            4'd4:out=e;
            4'd5:out=f;
            4'd6:out=g;
            4'd7:out=h;
            4'd8:out=i;
            default:out=16'hffff;
        endcase       
    end
        
endmodule

Mux256to1

Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

Expected solution length: Around 1 line.

Write your solution here

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    //integer i;
    //always @(*) begin
    //   for(i=0;i<256;i++)
    //        if(sel==i)
    //            out=in[i];
    //end
    assign out = in[sel];
    
endmodule

Mux256to1v

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

Expected solution length: Around 1–5 lines.

Write your solution here

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );

    //注意这种用法会出错：assign out = in[sel*4+3:sel*4];
    assign out = {in[sel*4+3],in[sel*4+2],in[sel*4+1],in[sel*4]};
    
endmodule