目录
Count15
Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.
Write your solution here
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always@(posedge clk) begin
if(reset)
q <= 4'd0;
else if(q == 4'd15)
q <= 4'd0;
else
q <= q+1;
end
endmodule
Count10
Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0.
Write your solution here
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:0] q);
always@(posedge clk) begin
if(reset)
q <= 4'd0;
else if(q == 4'd9)
q <= 4'd0;
//第九个时钟周期（q==9）先把0存入寄存器，下个周期（第十个时钟周期）把寄存器的值给q
else
q <= q+1;
end
endmodule
Count1to10
Make a decade counter that counts 1 through 10, inclusive. The reset input is synchronous, and should reset the counter to 1.
Write your solution here
module top_module (
input clk,
input reset,
output [3:0] q);
initial begin
q=1;
end
always@(posedge clk) begin
if(reset)
q <= 4'd1;
else if(q == 4'd10)
q <= 4'd1;
else
q <= q+1;
end
endmodule
Countslow
Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.
Write your solution here
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always@(posedge clk) begin
if(reset)
q <= 4'd0;
else if(slowena==0)
q <= q;
else if(q == 4'd9)
q <= 4'd0;
else
q <= q+1;
end
endmodule
Exams/ece241 2014 q7a
Design a 1-12 counter with the following inputs and outputs:
- Reset Synchronous active-high reset that forces the counter to 1
- Enable Set high for the counter to run
- Clk Positive edge-triggered clock input
- Q[3:0] The output of the counter
- c_enable, c_load, c_d[3:0] Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:
- the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). The count4 module is provided to you. Instantiate it in your circuit.
- logic gates
module count4( input clk, input enable, input load, input [3:0] d, output reg [3:0] Q );
The c_enable, c_load, and c_d outputs are the signals that go to the internal counter's enable, load, and d inputs, respectively. Their purpose is to allow these signals to be checked for correctness.
Write your solution here
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
/*
module count4(
input clk,
input enable,
input load,
input [3:0] d,
output reg [3:0] Q
);
*/
//我们需要做的不是自己设计一个计数器，而是需要例化题目给的一个计数器，
//题目给的计数器需要有一个输入信号为load信号，计数到12并且enable为高时，回到初值
always@(*) begin
if(reset) begin//相当于if的花括号
c_load <=1;
c_d <= 3'd1;
end
else begin
if(Q == 4'd12 && enable) begin
c_load <= 1'b1;
c_d <= 3'd1;
end
else begin
c_load <= 1'b0;
c_d <= 3'd0;
end
end
end
assign c_enable = enable;
count4 the_counter (clk, c_enable, c_load, c_d ,Q );
endmodule
Exams/ece241 2014 q7b
From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used to drive an Enable signal for a set of hour/minute/second counters to create a digital wall clock. Since we want the clock to count once per second, the OneHertz signal must be asserted for exactly one cycle each second. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).
The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.
module bcdcount ( input clk, input reset, input enable, output reg [3:0] Q );
Write your solution here
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
/*
module bcdcount (
input clk,
input reset,
input enable,
output reg [3:0] Q
);
*/
//题目提供的BCD计数器，例化成为个位计数器、十位计数器、百位计数器。
//个位计数器计数到9，进位到十位计数器，十位计数器计数到9，进位到百位计数器，直到计数到999为止。
wire [3:0] Q1,Q2,Q3;
assign c_enable = {Q1 == 4'd9 && Q2 == 4'd9 ,Q1 == 4'd9 ,1'b1};
assign OneHertz = {Q1 == 4'd9 && Q2 == 4'd9 && Q3 == 4'd9};
bcdcount counter0 (clk, reset, c_enable[0], Q1);//最快
bcdcount counter1 (clk, reset, c_enable[1], Q2);
bcdcount counter2 (clk, reset, c_enable[2], Q3);//最慢
endmodule
Countbcd
Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented.
You may want to instantiate or modify some one-digit decade counters.
Write your solution here
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q);
always@(posedge clk) begin
if(reset)
q <= 0;
else begin
if(q[3:0] == 4'd9 && q[7:4] == 4'd9 && q[11:8] == 4'd9 && q[15:12] == 4'd9) begin
q <= 0;
end
else if(q[3:0] == 4'd9 && q[7:4] == 4'd9 && q[11:8] == 4'd9) begin
q[11:0] <= 8'd0;
q[15:12] <= q[15:12]+1;
end
else if(q[3:0] == 4'd9 && q[7:4] == 4'd9) begin
q[7:0] <= 8'd0;
q[11:8] <= q[11:8]+1;
end
else if(q[3:0] == 4'd9)begin
q[3:0] <= 4'd0;
q[7:4] <= q[7:4]+1;
end
else begin
q <= q+1;
end
end
end
assign ena[1]=(q[3:0]==4'd9)?1:0;//这样可以防止慢一拍（如果放在if==9里面和结果对比慢一拍）
assign ena[2]=(q[7:4]==4'd9&&q[3:0] == 4'd9)?1:0;
assign ena[3]=(q[3:0] == 4'd9 && q[7:4] == 4'd9 && q[11:8] == 4'd9)?1:0;
endmodule
Count clock
Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).
reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.
The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.
Write your solution here
module top_module(
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss);
//’b:二进制
//‘h:十六进制
//'d:十进制
always@(posedge clk) begin
if(reset == 1) begin
hh <= 8'h12;
mm <= 0;
ss <= 0;
pm <= 0;
end
else if(hh[7:4] == 1 && hh[3:0] == 1 && mm[7:4] == 5 && mm[3:0] == 9 && ss[7:4] == 5 && ss[3:0] == 9 && ena == 1) begin
pm <= ~pm;
hh[3:0] <= 2;
mm <= 0;
ss <= 0;
end
else if(hh[7:4] == 1 && hh[3:0] == 2 && mm[7:4] == 5 && mm[3:0] == 9 && ss[7:4] == 5 && ss[3:0] == 9 && ena == 1) begin
hh <= 1;
mm <= 0;
ss <= 0;
end
else if(hh[3:0] == 9 && mm[7:4] == 5 && mm[3:0] == 9 && ss[7:4] == 5 && ss[3:0] == 9 && ena == 1) begin
hh[7:4] <= hh[7:4]+1;
hh[3:0] <= 0;
mm <= 0;
ss <= 0;
end
else if(mm[7:4] == 5 && mm[3:0] == 9 && ss[7:4] == 5 && ss[3:0] == 9 && ena == 1) begin
hh[3:0] <= hh[3:0]+1;
mm <= 0;
ss <= 0;
end
else if(mm[3:0] == 9 && ss[7:4] == 5 && ss[3:0] == 9 && ena == 1) begin
mm[7:4] <= mm[7:4]+1;
mm[3:0] <= 0;
ss <= 0;
end
else if(ss[7:4] == 5 && ss[3:0] == 9 && ena == 1) begin
mm[3:0] <= mm[3:0]+1;
ss <= 0;
end
else if(ss[3:0] == 9 && ena == 1) begin
ss[7:4] <= ss[7:4]+1;
ss[3:0] <= 0;
end
else if(ena == 1)
ss[3:0] <= ss[3:0]+1;
end
endmodule
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