目录
Shift4
Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.
- areset: Resets shift register to zero.
- load: Loads shift register with data[3:0] instead of shifting.
- ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
- q: The contents of the shift register.
If both the load and ena inputs are asserted (1), the load input has higher priority.
Write your solution here
module top_module(
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q);
//异步复位 同步加载
always@(posedge clk or posedge areset) begin
if(areset == 1)
q <= 0;
else if(load == 1)
q[3:0] <= data[3:0];
else if(ena == 1)
q[3:0] <= {1'b0,q[3],q[2],q[1]};
//拼接语句需要标注位宽，默认不会为1，所以 0 写成 1b'0
end
endmodule
Rotate100
Build a 100-bit left/right rotator, with synchronous load and left/right enable. A rotator shifts-in the shifted-out bit from the other end of the register, unlike a shifter that discards the shifted-out bit and shifts in a zero. If enabled, a rotator rotates the bits around and does not modify/discard them.
- load: Loads shift register with data[99:0] instead of rotating.
- ena[1:0]: Chooses whether and which direction to rotate.
- 2'b01 rotates right by one bit
- 2'b10 rotates left by one bit
- 2'b00 and 2'b11 do not rotate.
- q: The contents of the rotator.
Write your solution here
module top_module(
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q);
always@(posedge clk) begin
if(load)
q <= data;
else
case(ena)
2'b01: q[99:0] <= {q[0],q[99:1]};//rotates right by one bit
2'b10: q <= {q[98:0],q[99]};//rotates left by one bit
default: q <= q;//2'b00 and 2'b11 do not rotate.
endcase
end
endmodule
Shift18
Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.
There is no difference between logical and arithmetic left shifts.
- load: Loads shift register with data[63:0] instead of shifting.
- ena: Chooses whether to shift.
- amount: Chooses which direction and how much to shift.
- 2'b00: shift left by 1 bit.
- 2'b01: shift left by 8 bits.
- 2'b10: shift right by 1 bit.
- 2'b11: shift right by 8 bits.
- q: The contents of the shifter.
Write your solution here
module top_module(
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q);
always@(posedge clk) begin
if(load)
q <= data;
else if(ena)
case(amount)
2'b00:q[63:0] <= {q[62:0],1'b0};//2'b00: shift left by 1 bit.
2'b01:q[63:0] <= {q[55:0],8'b0};//2'b01: shift left by 8 bits.
//有符号数需要考虑算数右移
//符号数，算数左移与逻辑左移一致，移位后补0；算数右移与逻辑右移不同，算数右移左侧需补充符号位而非0
//即补最左边的符号位替代0
2'b10:q[63:0] <= {q[63],q[63:1]};//2'b10: shift right by 1 bit.
2'b11:q[63:0] <= {{8{q[63]}},q[63:8]};//2'b11: shift right by 8 bits.
default: q <= q;
endcase
end
endmodule
Lfsr5
A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2n-1 states before repeating (the all-zero state is never reached).
The following diagram shows a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. (Tap positions are usually numbered starting from 1). Note that I drew the XOR gate at position 5 for consistency, but one of the XOR gate inputs is 0.
Build this LFSR. The reset should reset the LFSR to 1.
Write your solution here
module top_module(
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
reg flag,qq0,qq3;
assign flag = q[0];
assign qq0 = flag^0;
assign qq3 = flag^q[3];
always@(posedge clk) begin
if(reset)
q <= 1;
else
q[4:0] <= {qq0,q[4],qq3,q[2:1]};
end
endmodule
Mt2015 lfsr
Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdff
Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR.
Write your solution here
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR); // Q
reg Q0,Q1,Q2,Q11;
assign Q11 = Q1^Q2;
assign LEDR[2:0] = {Q2,Q1,Q0};
DQ inst1(KEY[0],KEY[1],SW[0],Q2,Q0);
DQ inst2(KEY[0],KEY[1],SW[1],Q0,Q1);
DQ inst3(KEY[0],KEY[1],SW[2],Q11,Q2);
endmodule
module DQ (
input clk, // KEY[0]
input L, // KEY[1]
input r_in,// R 0 1 2
input q_in,// Q 0 1 2
output reg Q);
always@(posedge clk)
if(L)
Q<=r_in;
else
Q<=q_in;
endmodule
Lfsr32
See Lfsr5 for explanations.
Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1.
Write your solution here
module top_module(
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg qq32,qq22,qq2,qq1;//32, 22, 2, and 1.
assign qq32 = q[0]^0;
assign qq22 = q[0]^q[22];
assign qq2 = q[0]^q[2];
assign qq1 = q[0]^q[1];
always@(posedge clk) begin
if(reset)
q <= 32'h1;
else
q[31:0] <= {qq32,q[31:23],qq22,q[21:3],qq2,qq1};
end
endmodule
Exams/m2014 q4k
Implement the following circuit:
Write your solution here
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
wire Q1,Q2,Q3;
DQ inst1(clk,resetn,in,Q1);
DQ inst2(clk,resetn,Q1,Q2);
DQ inst3(clk,resetn,Q2,Q3);
DQ inst4(clk,resetn,Q3,out);
endmodule
module DQ (
input clk,
input resetn, // synchronous reset
input in,
output Q);
always@(posedge clk) begin
if(~resetn)
Q <= 0;
else
Q <= in;
end
endmodule
Exams/2014 q4b
Consider the n-bit shift register circuit shown below:
Write a top-level Verilog module (named top_module) for the shift register, assuming that n = 4. Instantiate four copies of your MUXDFF subcircuit in your top-level module. Assume that you are going to implement the circuit on the DE2 board.
- Connect the R inputs to the SW switches,
- clk to KEY[0],
- E to KEY[1],
- L to KEY[2], and
- w to KEY[3].
- Connect the outputs to the red lights LEDR[3:0].
(Reuse your MUXDFF from exams/2014_q4a.)
Write your solution here
module top_module (
input [3:0] SW,// Connect the R inputs to the SW switches,
input [3:0] KEY,//clk to KEY[0],E to KEY[1],L to KEY[2], and w to KEY[3].
output [3:0] LEDR//Connect the outputs to the red lights LEDR[3:0].
); //
wire Q3,Q2,Q1,Q0;
assign LEDR[3:0] = {Q3,Q2,Q1,Q0};
MUXDFF inst1(KEY[0],KEY[3],KEY[1],SW[3],KEY[2],Q3);
MUXDFF inst2(KEY[0],Q3,KEY[1],SW[2],KEY[2],Q2);
MUXDFF inst3(KEY[0],Q2,KEY[1],SW[1],KEY[2],Q1);
MUXDFF inst4(KEY[0],Q1,KEY[1],SW[0],KEY[2],Q0);
endmodule
module MUXDFF (input clk,input w,input E,input R,input L,output Q);
wire sel1,sel2;
assign sel1 = E?w:Q;
assign sel2 = L?R:sel1;
always@(posedge clk) begin
Q <= sel2;
end
endmodule
Exams/ece241 2013 q12
In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is "random access", as in a typical RAM. You will then use the circuit to realize a 3-input logic function.
First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be called S, which feeds the input of Q[0] (MSB is shifted in first). The enable input controls whether to shift. Then, extend the circuit to have 3 additional inputs A,B,C and an output Z. The circuit's behaviour should be as follows: when ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).
Write your solution here
module top_module (
input clk, //
input enable, //enable input controls whether to shift
input S, //input should be called S
input A, B, C,//ABC is 000, Z=Q[0], when ABC is 001, Z=Q[1]
output Z );
reg [7:0] Q;
always@(*) begin //如果是 posedge clk 结果比答案慢一拍
case({A,B,C})
3'b000:Z <= Q[0];
3'b001:Z <= Q[1];
3'b010:Z <= Q[2];
3'b011:Z <= Q[3];
3'b100:Z <= Q[4];
3'b101:Z <= Q[5];
3'b110:Z <= Q[6];
3'b111:Z <= Q[7];
default:Z <= Z;
endcase
end
always@(posedge clk) begin
if(enable)
Q[7:0] <= {Q[6:0],S};//移位
end
endmodule
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