在远程FPGA虚拟实验平台上实现多功能运算器

多功能运算电路

电路图

要认真观察电路图，在代码的电路描述模块要对照电路图进行电路设计。

功能表

设计代码前要补全该功能表，这样在验证时就会方便很多。

VirtualBoard模块代码

端口描述

`default_nettype none 
module VirtualBoard (
    input  logic  CLOCK,      // 10 MHz Input Clock 
    input  logic [19:0] PB,   // 20 Push Buttons, logical 1 when pressed
    input  logic [35:0] S,    // 36 Switches
    output logic [35:0] L,    // 36 LEDs, drive logical 1 to light up
    output logic  [7:0] SD7,  // 8 common anode Seven-segment Display
    output logic  [7:0] SD6,
    output logic  [7:0] SD5,
    output logic  [7:0] SD4,
    output logic  [7:0] SD3,
    output logic  [7:0] SD2,
    output logic  [7:0] SD1,
    output logic  [7:0] SD0
); 

输入端口描述

/** The input port is replaced with an internal signal **/
wire [3:0]M= S[12:9];
wire [3:0] X = S[7:4];
wire [3:0] Y = S[3:0];
wire SL=S[13];
wire SV=S[14];
wire SR=S[15];
wire Cin=S[8];

电路描述

/************* The logic of this experiment *************/
wire [3:0] A,B,F;
wire C0;
wire sign, zero, overflow, carryOut;

assign A[3] = (X[3]&SR)|(X[3]&SV)|(X[2]&SL);
assign A[2] = (X[3]&SR)|(X[2]&SV)|(X[1]&SL);
assign A[1] = (X[2]&SR)|(X[1]&SV)|(X[0]&SL);
assign A[0] = (X[1]&SR)|(X[0]&SV)|(0&SL);
assign B[3] = (Y[3]&M[0])|(~Y[3]&M[1]);
assign B[2] = (Y[2]&M[0])|(~Y[2]&M[1]);
assign B[1] = (Y[1]&M[0])|(~Y[1]&M[1]);
assign B[0] = (Y[0]&M[0])|(~Y[0]&M[1]);
assign C0 = (M[3]&Cin&M[0])|M[2]|(M[3]&M[1]&(~Cin));

assign {carryOut,F[3:0]} = A + B + C0;  
assign sign = F[3];
assign zero = (F==0) ? 1 : 0;  // ~|F;
assign overflow = (~A[3]) & ~B[3] & F[3] | (A[3]) & B[3] & ~F[3] ;

输出端口描述

/****** Internal signal assign to output port *******/
assign L[3:0]  = B[3:0];
assign L[7:4]  = A[3:0]; 
assign L[12:9] = F[3:0];
assign L[26] = C0; 
assign L[21:18] = {sign, zero, overflow, carryOut};

endmodule

测试，提交

在远程FPGA虚拟实验平台上下载电路及相应的rbf文件，按功能运行电路，在关键步骤进行说明，最后按要求提交文件。