VERILOG实现四位七段数码管显示

最新推荐文章于 2024-09-14 12:45:00 发布

lyqdy

最新推荐文章于 2024-09-14 12:45:00 发布

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分类专栏： FPGA学习文章标签： verilog 数码管扫描

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//
//filename:	dyp.v
//author:	lyq
//Date: 	2016.3.2 9:36
//
//Lattice XP2-17 DEMO BOARD
//4位七段带小数点数码管显示控制模块
//
//clk: 50M
//d1~d4, d[7]-dp, d[6:0]-ASCII or digit
//sel[3:0]: 位选
//seg[7:0]: 段码 a~g, dp
//
module dpy_mod(clk, d1, d2, d3, d4, sel, seg);
input clk;
input [7:0] d1, d2, d3, d4; //d[7]-dp, d[6:0]-ASCII
output reg [3:0] sel;
output reg [7:0] seg;	//a~g,dp

//扫描频率:50Hz
parameter update_interval = 50000000 / 200 - 1;

reg [7:0] dat;

reg [1:0] cursel;
integer selcnt;

//扫描计数，选择位
always @(posedge clk)
begin
	selcnt <= selcnt + 1;
		
	if (selcnt == update_interval)
	begin
		selcnt <= 0;
		cursel <= cursel + 1;
	end
end

//切换扫描位选线和数据
always @(*)
begin
	sel = 4'b0000;
	case (cursel)
		2'b00: begin dat = d1; sel = 4'b1000; end
		2'b01: begin dat = d2; sel = 4'b0100; end
		2'b10: begin dat = d3; sel = 4'b0010; end
		2'b11: begin dat = d4; sel = 4'b0001; end
	endcase
end

//更新段码
always @(*)
begin
	seg[0] <= ~dat[7]; //dp
	case (dat[6:0])
		7'h00 	: seg[7:1] <= 7'b0000001;	//0
		7'h01 	: seg[7:1] <= 7'b1001111;	//1
		7'h02 	: seg[7:1] <= 7'b0010010;	//2
		7'h03 	: seg[7:1] <= 7'b0000110;	//3
		7'h04 	: seg[7:1] <= 7'b1001100;	//4
		7'h05 	: seg[7:1] <= 7'b0100100;	//5
		7'h06 	: seg[7:1] <= 7'b0100000;	//6
		7'h07 	: seg[7:1] <= 7'b0001111;	//7
		7'h08 	: seg[7:1] <= 7'b0000000;	//8
		7'h09 	: seg[7:1] <= 7'b0000100;	//9
		7'h30 	: seg[7:1] <= 7'b0000001;	//'0'
		7'h31 	: seg[7:1] <= 7'b1001111;	//'1'
		7'h32 	: seg[7:1] <= 7'b0010010;	//'2'
		7'h33 	: seg[7:1] <= 7'b0000110;	//'3'
		7'h34 	: seg[7:1] <= 7'b1001100;	//'4'
		7'h35 	: seg[7:1] <= 7'b0100100;	//'5'
		7'h36 	: seg[7:1] <= 7'b0100000;	//'6'
		7'h37 	: seg[7:1] <= 7'b0001111;	//'7'
		7'h38 	: seg[7:1] <= 7'b0000000;	//'8'
		7'h39 	: seg[7:1] <= 7'b0000100;	//'9'
		default : seg[7:1] <= 7'b0110000; 	//E-rror
	endcase
end
	
endmodule