2020-10-18
`timescale 1ns / 1ps
module bin_dec(clk,bin,rst_n,one,ten,hun,count,shift_reg
);
input [7:0] bin;
input clk,rst_n;
output [3:0] one,ten;
output [3:0] count;
output [1:0] hun;
output [17:0]shift_reg;
reg [3:0] one,ten;
reg [1:0] hun;
reg .
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2022-05-16 11:15:15 ·
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