m0_37753944的博客

`timescale 1ns / 1psmodule bin_dec(clk,bin,rst_n,one,ten,hun,count,shift_reg );input [7:0] bin;input clk,rst_n;output [3:0] one,ten;output [3:0] count;output [1:0] hun;output [17:0]shift_reg;reg [3:0] one,ten;reg [1:0] hun;reg .