HDLbits Lemmings4 Lemming 游戏最终版 verilog fpga

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    input dig,
    output walk_left,
    output walk_right,
    output aaah,
    output digging ); 
	parameter left = 0, right = 1, ldown = 2, rdown = 3, ldig = 4,rdig = 5;
	parameter down_too_long = 6,die = 7;
    reg [2:0]state;
    reg [2:0]next_state;
	reg [5:0]down_time;
    
    
    always@(posedge clk or posedge areset)begin
        if(areset)begin
            down_time <= 0;
        end
        else if(next_state == ldown || next_state == rdown)begin
            down_time <= down_time + 1;
        end
        else begin
            down_time <= 0;
        end
    end

    always@(posedge clk or posedge areset)begin
        if(areset)begin
        	state <= left;
        end
        else begin
				state <= next_state;
        end
    end
    
	always@(*)begin
		case(state)
            left:next_state = ground?(dig?ldig:(bump_left?right:left)):ldown;
            right:next_state = ground?(dig?rdig:(bump_right?left:right)):rdown;
            ldown:next_state = ground?left:((down_time == 20)?down_too_long:ldown);
            rdown:next_state = ground?right:((down_time == 20)?down_too_long:rdown);
			ldig:next_state = ground?ldig:ldown;
			rdig:next_state = ground?rdig:rdown;
			down_too_long:next_state = (ground)?die:down_too_long;
			die:next_state = die;
		endcase
	end
	
	always@(*)begin
		case(state)
		left:{walk_left,walk_right,aaah,digging}=4'b1000;
		right:{walk_left,walk_right,aaah,digging}=4'b0100;
		ldown:{walk_left,walk_right,aaah,digging}=4'b0010;
		rdown:{walk_left,walk_right,aaah,digging}=4'b0010;
		ldig:{walk_left,walk_right,aaah,digging}=4'b0001;
		rdig:{walk_left,walk_right,aaah,digging}=4'b0001;
		down_too_long:{walk_left,walk_right,aaah,digging}=4'b0010;
		die:{walk_left,walk_right,aaah,digging}=4'b0000;
        endcase
	end
	
    
endmodule