2021-08-11

八位加法器

verilog

module adder_1(

	input a,
	input b,
	input ci,
	output y,
	output co
	);
	 //--statements--//
	 
	 //--data fiow--//
	 //assign y = ((~a)&(~b)&ci) | ((~a)&b&(~ci)) | (a&(~b)&(~ci)) | (a&b&ci);
	 //assign co = ((~a)&b&ci) | (a&(~b)&ci) | (a&b&(~ci)) | (a&b&ci);  
	
	//wire s1,t1,t2,t3;
	
	//assign s1=a^b;
	//assign y=ci^s1;
	
	//assign t1=a&b;
	//assign t2=b&ci;
	//assign t3=a&ci;
	//assign co=t1|t2|t3;
	
	
	//--structrization--//
	//xor x1(s1,a,b);
	//xor x2(y,s1,ci);
	//and A1(t3,a,b);
	//and A2(t2,b,ci);
	//and A3(T1,A,CI);
	
	//or O1(co,ti,t2,t3);
	
	
	//--behavior--//
	reg y,co;
	reg t1,t2,t3;
	
	always @(a or b or ci)
	begin
		y =(a^b)^ci;
		
		t1=a&b;
		t2=a&ci;
		t3=b&ci;
		
		co=t1|(t2|t3);
	end
		

module adder_4(
    
	input [3:0] a,
	input [3:0] b,
	input ci,
	output [3:0]y,
	output co
	);
	
	wire c,d,e;
	
	adder_1 adder_1_inst_0(

	.a    (a[0]),
	.b    (b[0]),
	.ci   (ci)  ,
	.y    (y[0]),
	.co   (c)   
	);

	adder_1 adder_1_inst_2(

	.a    (a[1]),
	.b    (b[1]),
	.ci   (c),
	.y    (y[1]),
	.co   (d)
	);
	
	adder_1 adder_1_inst_3(

	.a    (a[2]),
	.b    (b[2]),
	.ci   (d),
	.y    (y[2]),
	.co   (e) 
	);
	
	adder_1 adder_1_inst_4(

	.a    (a[3]),
	.b    (b[3]),
	.ci   (e),
	.y    (y[3]),
	.co   (co)
	);
endmodule

module adder_8(

   
	input [7:0] a,
	input [7:0] b,
	input ci,
	output [7:0] y,
	output co
	);
	wire e;

	adder_4 adder_4_inst_low(
    
	.a     (a[3:0]) ,
	.b     (b[3:0]) ,
	.ci    (ci) ,
	.y     (y[3:0]) ,
	.co    (e)
	);
	
	adder_4 adder_4_inst_high(
    
	.a     (a[7:4])  ,
	.b     (b[7:4])   ,
	.ci    (e)       ,
	.y     (y[7:4])  ,
	.co    (co)
	);
endmodule

module adder_8_tb;

	// Inputs
	reg [7:0] a;
	reg [7:0] b;
	reg ci;

	// Outputs
	wire [7:0] y;
	wire co;

	// Instantiate the Unit Under Test (UUT)
	adder_8 adder_8_inst(
		.a(a), 
		.b(b), 
		.ci(ci), 
		.y(y), 
		.co(co)
	);

	initial begin
		// Initialize Inputs
		repeat(100) begin
		a = {$random}%256;
		b = {$random}%256;
		ci = 0;

		// Wait 100 ns for global reset to finish
		#100;
       end 
		// Add stimulus here
	end
	
      
endmodule

vhdl

not