2021-08-14

流水灯4个

verilog

module led(
	input wire clk,
	input wire rst_n,
	
	output reg [3:0] led
	
	);
	
	parameter t = 50_000_000;
	
	wire [27:0] cnt;
	
	always @ (posedge clk,negedge rst_n)
	begin
		if(rst_n == 1'b0)
		  cnt <= 28'd0;
		else if(cnt == 4*t - 1)
		  cnt <= 28'd0;
		else
		  cnt <= cnt + 1'b1;
	end
	
	always @ (posedge clk,negedge rst_n)
	begin
	  if(rst_n == 1'b0)
	    flag <= 1'b0;
	  else if(cnt == 4*t - 1)
		flag <= 1'b1;
	  else
	    flag <= 1'b0;
	end
	
	always @ (posedge clk,negedge rst_n)
	begin
		if (rst == 1'b0)
		  led <= 4'b0001;
		else if (cnt <= t - 1)
		  led <= 4'b0001;
		else if (cnt <= 2 * t - 1)
		  led <= 4'b0010;
		else if (cnt <= 3 * t - 1)
		  led <= 4'b0100;
		else 
		  led <= 4'b1000;
	end
		
		
		
		
endmodule