基于FPGA的出租车计费系统，用Quartus2，VHDL语言实现，附源代码，一定能实现

基于FPGA的出租车计费系统，用Quartus2，VHDL语言实现，附源代码，一定能实现

大家得先学会quartus 2的基本操作，文件名记得与代码同名，若要烧录，先引脚锁定,烧录可能无法识别USB，去百度如何更新驱动即可解决。一定先去B站学会基本操作，代码一定一定没有问题。
1设计作品概述
作品为一种的士计费器。采用开发板的时钟代表车轮传感器的输出脉冲（每转一圈，输出一个脉冲上升沿），对脉冲进行计数就可以实现计程、计费。其计程和计费的主要原则是：车起步后开始计费，首先显示起步价（本次设计起步费为7.0元），车在行驶3km以内，只收起步价7.0元；车行驶超过3km后，按每公里2.2元计费（在7.0元基础上每行驶1km车费加2.2元），车费依次累加；行驶路程达到或超过9km后(车费达到20元)，每公里加收50%的车费，车费变成按每公里3.3元开始计费。车暂时停止（行驶中遇红灯或中途暂时停车）不计费，车费保持不变。若停止则车费清零，等待下一次计费的开始。
计费和计程结果用开发板上数码管显示（同时显示计程和计费的结果），计费和计程结果分别用3个数码管来显示。从左往右前三个数码管显示费用，单位元；从左往右后三个数码管显示行驶距离，单位千米。最大有效记录行驶距离为305千米。

根据源代码进行的仿真。

分频

计程

计费![

计费转码

译码![在这里插入图片描述](https://img-blog.csdnimg.cn/20210105121530896.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_
,size_16,color_FFFFFF,t_70)

附录：源代码
顶层文件：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jifeiqi is
port(clk,res,key1:in std_logic;
se:out std_logic_vector(5 downto 0);
led:out std_logic_vector(3 downto 0);
le:out std_logic_vector(7 downto 0));
end entity;
architecture one of jifeiqi is
component jicheng
port(clk,res:in std_logic;
counter:out integer range 0 to 99);
end component;
component jifei
port(counter:in integer range 0 to 99;
yuan:out integer range 0 to 3172);
end component;
component jichengzhuanma
port(counter:in integer range 0 to 99;
clk,res:in std_logic;
q0,q1:out std_logic_vector(3 downto 0));
end component;
component jifeizhuanma
port(yuan:in integer range 0 to 3172;
clk,res:in std_logic;
p0,p1,p2,p3:out std_logic_vector(3 downto 0));
end component;
component frediv
port (clk,key1,res:in std_logic;
clkled:out std_logic;
clkr:out std_logic;
clkn:out std_logic);
end component;
component yima
port(clk:in std_logic;
s0,s1,m0,m1,m2,m3:in std_logic_vector(3 downto 0);
sel:out std_logic_vector(5 downto 0);
led:out std_logic_vector(7 downto 0));
end component;
signal s0,s1,m0,m1,m2,m3: std_logic_vector(3 downto 0);
signal clkr,clkn,clkled:std_logic;
signal counters:integer range 0 to 99;
signal counter:integer range 0 to 99;
signal yuans:integer range 0 to 3172;
begin
led<=s0;
u0: frediv port map(clk,key1,res,clkled,clkr,clkn);
u1: jicheng port map(clkn,res,counters);
u2: jifei port map(counters,yuans);
u3: jichengzhuanma port map(counters,clk,res,s0,s1);
u4: jifeizhuanma port map(yuans,clk,res,m0,m1,m2,m3);
u5: yima port map(clkled,s0,s1,m0,m1,m2,m3,se,le);
end;

分频
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity frediv is
port (clk,key1,res:in std_logic;
clkled:out std_logic;
clkr:out std_logic;
clkn:out std_logic);
end;
architecture one of frediv is
TYPE states is (run,stop);
signal cs,next_state:states:=run;
signal on_off:std_logic;
signal clk1,clk2,clk3:std_logic;
begin
COM:process(cs) begin
case cs is
when run=>on_off<=‘0’;next_state<=stop;
when stop=>on_off<=‘1’;next_state<=run;
end case;
end process;
REG:process(res,key1) begin
if res=‘0’ then cs<=run;
elsif key1=‘0’ then cs<=next_state;
end if;
end process;
process(clk,on_off)
variable counter:integer range 0 to 49999;
begin
IF (clk’EVENT AND clk=‘1’ and on_off=‘0’) THEN
IF counter<=24999 THEN
clk2<=‘0’;
counter:=counter+1;
ELSIF counter>=2499 AND counter<=49999 THEN
clk2<=‘1’;
counter:=counter+1;
ELSE counter:=0;
END IF;
END IF;
end process;
clkr<=clk2;
process(clk2)
variable counter:integer range 0 to 999;
begin
IF clk2’EVENT AND clk2=‘1’ THEN
IF counter<=499 THEN
clk1<=‘0’;
counter:=counter+1;
ELSIF counter>=499 AND counter<=999 THEN
clk1<=‘1’;
counter:=counter+1;
ELSE counter:=0;
END IF;
END IF;
end process;
clkn<=clk1;
process(clk)
variable counter:integer range 0 to 49999;
begin
IF (clk’EVENT AND clk=‘1’) THEN
IF counter<=24999 THEN
clk3<=‘0’;
counter:=counter+1;
ELSIF counter>=2499 AND counter<=49999 THEN
clk3<=‘1’;
counter:=counter+1;
ELSE counter:=0;
END IF;
END IF;
end process;
clkled<=clk3;
end;

计程：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jicheng is --对1秒为周期的时钟计数，最大值为1000
port(clk,res:in std_logic;
counter:out integer range 0 to 99);
end;
architecture one of jicheng is
signal qq:integer range 0 to 99;
begin
process(clk,res)
begin
if res=‘0’ or qq=99 then
qq<=0;
elsif clk’event and clk=‘0’ then
qq<=qq+1;
end if;
end process;
counter<=qq;
end;

计费：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jifei is
port(counter:in integer range 0 to 99;
yuan:out integer range 0 to 3172);
end;
architecture one of jifei is
signal y:integer range 0 to 3172;
begin
process(counter)
Begin
if (counter=0) then
y<=0;
elsif (counter>0 and counter<=3) then
y<=70;
elsif (counter>3 and counter<=9) then
y<=70+22*(counter-3);
elsif (counter>9) then
y<=202+33*(counter-9);
end if;
end process;
yuan<=y-1;
end;

计费转码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jifeizhuanma is
port(yuan:in integer range 0 to 3172;
clk,res:in std_logic;
p0,p1,p2,p3:out std_logic_vector(3 downto 0));
end;
architecture one of jifeizhuanma is
begin
process(clk,res)
variable b0,b1,b2,b3:std_logic_vector(3 downto 0);
variable bb:integer range 0 to 3172;
begin
if res=‘0’ then
bb:=0; b0:=“0000”;b1:=“0000”;b2:=“0000”;b3:=“0000”;
elsif clk’event and clk=‘1’ then
if bb<=yuan then
if (b0=9 and b1=9 and b2=9)then
b3:=b3+1;
b2:=“0000”;
b1:=“0000”;
b0:=“0000”;
bb:=bb+1;
elsif (b0=9 and b1=9)then
b2:=b2+1;
b0:=“0000”;
b1:=“0000”;
bb:=bb+1;
elsif (b0=9 )then
b1:=b1+1;
b0:=“0000”;
bb:=bb+1;
else
b0:=b0+1;
bb:=bb+1;
end if;
else
p0<=b0; p1<=b1; p2<=b2; p3<=b3;
bb:=0; b0:=“0000”;b1:=“0000”;b2:=“0000”;b3:=“0000”;
end if;
end if;
end process;
end;

译码：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity yima is
port(clk:in std_logic;
s0,s1,m0,m1,m2,m3:in std_logic_vector(3 downto 0);
sel:out std_logic_vector(5 downto 0);
led:out std_logic_vector(7 downto 0));
end;

architecture one of yima is
begin
process(clk)
variable cnt:std_logic_vector(2 downto 0);
variable leds:std_logic_vector(3 downto 0);
begin
if clk’event and clk='1’then
if cnt<5 then
cnt:=cnt+1;
else cnt:=“000”;
end if;
case cnt is
when “000” => sel<=“111110”;leds:=s0;
when “001” => sel<=“111101”;leds:=s1;
when “010” => sel<=“111011”;leds:=m0;
when “011” => sel<=“110111”;leds:=m1;
when “100” => sel<=“101111”;leds:=m2;
when “101” => sel<=“011111”;leds:=m3;
when others=> null;
end case;
if cnt=“011” then
case leds is
when “0000” => led<=“01000000”;
when “0001” => led<=“01111001”;–显示1
when “0010” => led<=“00100100”;–显示2
when “0011” => led<=“00110000”;
when “0100” => led<=“00011001”;
when “0101” => led<=“00010010”;
when “0110” => led<=“00000010”;
when “0111” => led<=“01111000”;
when “1000” => led<=“00000000”;
when “1001” => led<=“00010000”;–显示9
when others => null;end case;
else
case leds is
when “0000” => led<=“11000000”;
when “0001” => led<=“11111001”;–显示1
when “0010” => led<=“10100100”;–显示2
when “0011” => led<=“10110000”;
when “0100” => led<=“10011001”;
when “0101” => led<=“10010010”;
when “0110” => led<=“10000010”;
when “0111” => led<=“11111000”;
when “1000” => led<=“10000000”;
when “1001” => led<=“10010000”;–显示9
when others => null;end case;
end if;
end if;
end process;
end;

链接：https://pan.baidu.com/s/1WlE3q6IzBPNK00JxPb2ovQ
提取码：xm0k
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资源绑定了，补上一块：

计程转码
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jichengzhuanma is
port(counter:in integer range 0 to 99;
clk,res:in std_logic;
q0,q1:out std_logic_vector(3 downto 0));
end;
architecture one of jichengzhuanma is

begin 

process(clk,res)
   variable a0,a1:std_logic_vector(3 downto 0);
	variable aa:integer range 0 to 99;

begin 
    if res='0' then
	    aa:=0; a0:="0000";a1:="0000";
	 elsif clk'event and clk='1' then
	    if aa<counter then
			 if(a0=9 )then
			         a1:=a1+1;
						a0:="0000";
					   aa:=aa+1;
			 else
			         a0:=a0+1;
					   aa:=aa+1;
		    end if;
			else
		            q0<=a0; q1<=a1;   
						aa:=0; a0:="0000";a1:="0000";
		 end if;
	  end if;
end process;

end;