Paper Reading: Eyeriss: An Energy-Efficient Reconfigurable Accelerator for DCNNs

1. Introduction

        This paper is published in JSSC in 2017. CNNs are widely used in modern AI systems but also bring challenges on throughput and energy efficiency to the underlying hardware. Therefore, the researchers design an energy-efficient reconfigurable accelerator, called Eyeriss.

2. Innovation points

        The Eyeriss system architecture is shown below.

         First, adopt a spatial architecture using an array of 168 processing elements (PEs) that creates a four-level memory hierarchy.

        Second, propose a processing dataflow, called row stationary. RS dataflow reconfigures the computation mapping of a given shape, which optimizes energy efficiency by maximally reusing data locally to reduce expensive data movement.

        Third, produce a network-on-chip (NoC) architecture.

        Fourth, adopt Run-length compression (RLC) and PE data gating techniques, which can improve energy efficiency.

3. Summary

        The die micrograph and chip specifications are shown below.