VHDL——1—8多路分配器

1.管脚图

多路分配器的作用：为输入信号选择输出

2.VHDL语言

library ieee;
use ieee.std_logic_1164.all;

entity dmux1to8 is
    port(data,enable : in std_logic;        --分别为输入端口和使能端口
	 s : in std_logic_vector(2 downto 0);   --选择信号端口
	 y0,y1,y2,y3,y4,y5,y6,y7:OUT STD_LOGIC  --输出端口     
	 );
end dmux1to8;

architecture behave of dmux1to8 is
begin 
  process(enable,s,data)
  begin	 
    if enable = '0' then
	   y0 <= '1';y1 <= '1';y2 <= '1';y3 <= '1';
      y4 <= '1';y5 <= '1';y6 <= '1';y7 <= '1';
	 elsif s = "000" then
	   y0 <= not (data);
	 elsif s = "001" then
		y1 <= not (data);
	 elsif s = "010" then
	   y2 <= not (data);
	 elsif s = "011" then
	   y3 <= not (data);
	 elsif s = "100" then
	   y4 <= not (data);
	 elsif s = "101" then
	   y5 <= not (data);
	 elsif s = "110" then
	   y6 <= not (data);
	 elsif s = "111" then
	   y7 <= not (data);
	 end if;
  end process;
end behave;