1.引脚图
a[7…0]和b[7…0]是被乘数和乘数输入端,q[15…0]是乘积输出端
2.VHDL语言
library ieee;
use ieee.std_logic_1164.all;
entity mul is
port(a,b : in integer range 0 to 255;
q : out integer range 0 to 65535);
end mul;
architecture behave of mul is
begin
q <= a*b;
end behave;