VHDL程序：四位乘法器

VHDL程序：四位乘法器

--1.  IF语句行为级描述

library  ieee;    
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multip_4 is
    port (a,b:in std_logic_vector(3 downto 0);
            y:out std_logic_vector(7 downto 0));
end multip_4;

architecture behave of multip_4 is
signal s0,s1,s2,s3:std_logic_vector(3 downto 0);
begin
    process(a,b,s0,s1,s2,s3)
    begin
     if b(0)='0' then s0<="0000";
     else s0<=a;
     end if;
     if b(1)='0' then s1<="0000";
     else s1<=a;
     end if;
     if b(2)='0' then s2<="0000";
     else s2<=a;
     end if;
     if b(3)='0' then s3<="0000";
     else s3<=a;
     end if;
     y<=("0000"&s0)+("000"&s1&'0')+("00"&s2&"00")+('0'&s3&"000");
    end process;
end behave;

--1.  IF语句行为级描述

library  ieee;    
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multip_4 is
    port (a,b:in std_logic_vector(3 downto 0);
            y:out std_logic_vector(7 downto 0));
end multip_4;

architecture behave of multip_4 is
signal s0,s1,s2,s3:std_logic_vector(3 downto 0);
begin
    process(a,b,s0,s1,s2,s3)
    begin
     if b(0)='0' then s0<="0000";
     else s0<=a;
     end if;
     if b(1)='0' then s1<="0000";
     else s1<=a;
     end if;
     if b(2)='0' then s2<="0000";
     else s2<=a;
     end if;
     if b(3)='0' then s3<="0000";
     else s3<=a;
     end if;
     y<=("0000"&s0)+("000"&s1&'0')+("00"&s2&"00")+('0'&s3&"000");
    end process;
end behave;

--2.  条件信号代入语句行为级描述

library  ieee;    
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multip_4 is
    port (a,b:in std_logic_vector(3 downto 0);
            y:out std_logic_vector(7 downto 0));
end multip_4;

architecture behave of multip_4 is
signal s1:std_logic_vector(3 downto 0);
signal s2:std_logic_vector(4 downto 0);
signal s3:std_logic_vector(5 downto 0);
signal s4:std_logic_vector(6 downto 0);
begin
    s1<=a when b(0)='1' else "0000";
    s2<=(a&'0')when b(1)='1'else"00000";
    s3<=(a&"00")when b(2)='1'else"000000";
    s4<=(a&"000")when b(3)='1'else"0000000";
    y<=s1+s2+s3+('0'&s4);
end behave;

--2.  条件信号代入语句行为级描述

library  ieee;    
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multip_4 is
    port (a,b:in std_logic_vector(3 downto 0);
            y:out std_logic_vector(7 downto 0));
end multip_4;

architecture behave of multip_4 is
signal s1:std_logic_vector(3 downto 0);
signal s2:std_logic_vector(4 downto 0);
signal s3:std_logic_vector(5 downto 0);
signal s4:std_logic_vector(6 downto 0);
begin
    s1<=a when b(0)='1' else "0000";
    s2<=(a&'0')when b(1)='1'else"00000";
    s3<=(a&"00")when b(2)='1'else"000000";
    s4<=(a&"000")when b(3)='1'else"0000000";
    y<=s1+s2+s3+('0'&s4);
end behave;