RISC-V 实现整数运算指令（Part 1）

 自己参考代码分析

验证I型运算指令

 

 源代码

package alu_defs;

   enum logic [3:0] {
      ADD = 4'b0001,
      SUB = 4'b0010,
      AND = 4'b0011,
      OR  = 4'b0100,
      XOR = 4'b0101,
      SRA = 4'b0110,
      SLL = 4'b0111,
      SRL = 4'b1000
   } aluop;

endpackage


`default_nettype none
// --------------------------------------------------------------------
// CPU 模块
// --------------------------------------------------------------------
module CPU
 #(
     parameter DATAWIDTH = 32,
     parameter ADDRWIDTH = 32
 )
(
    input  wire iCPU_Reset,
    input  wire iCPU_Clk,
    // 指令存储器接口
    output wire [ADDRWIDTH-1:0] oIM_Addr,   //指令存储器地址
    input  wire [DATAWIDTH-1:0] iIM_Data,   //指令存储器数据
    // 数据存储器接口
    input  wire [DATAWIDTH-1:0] iReadData,  //数据存储器读数据
    output wire [DATAWIDTH-1:0] oWriteData, //数据存储器写数据
    output wire [ADDRWIDTH-1:0] oAB,        //数据存储器地址
    output wire oWR,                        //数据存储器写使能
    // 连接调试器的信号
    output wire [ADDRWIDTH-1:0] oCurrent_PC,
    output wire oFetch,
    input  wire iScanClk,
    input  wire iScanIn,
    output wire oScanOut,
    input  wire [1:0] iScanCtrl
);

   /** The input port is replaced with an internal signal **/
   wire   clk   = iCPU_Clk;
   wire   reset = iCPU_Reset;

   // Instruction parts
   logic [31:0] pc, nextPC;
   logic [31:0] instruction; // instruction code
   assign nextPC = pc + 4;   /*-TODO 目前仅支持PC+4，增加分支指令时需修改 -*/
   // PC
   DataReg #(32) pcreg(.iD(nextPC), .oQ(pc), .Clk(clk), .Reset(reset), .Load(1'b1));
   assign oIM_Addr = pc;         // 连接指令存储器的地址端口
   assign instruction = iIM_Data;// 连接指令存储器的数据端口

   // Instruction decode
   logic [6:0] opcode;
   logic [2:0] funct3;
   logic [6:0] funct7;
   logic [4:0] ra1,ra2,wa;
   assign funct7 = instruction[31:25];
   assign ra2    = instruction[24:20];
   assign ra1    = instruction[19:15];
   assign funct3 = instruction[14:12];
   assign wa     = instruction[11:7];
   assign opcode = instruction[6:0];

   // Control unit
   logic cRegWrite;
   logic [3:0] aluOp;
   logic [4:0] cImm_type;  //{J,U,B,S,I}
   Controller controller(
      .iOpcode(opcode),
      .iFunct3(funct3),
      .iFunct7(funct7),
      /*-TODO 随着指令的增加，相应添加端口信号 -*/
      .oRegWrite(cRegWrite),
      .oImm_type(cImm_type),
      .oALUop(aluOp)
   );

   // Immediate data generation
   logic [31:0] immData;
   ImmGen  immGen(.iInstruction(instruction[31:7]),
      .iImm_type(cImm_type),
      .oImmediate(immData)
    );

   // Register file
   logic [31:0] regWriteData, regReadData1, regReadData2;
   RegisterFile #(32) regFile(.Clk(clk),
      .iWE(cRegWrite), .iWA(wa), .iWD(regWriteData),
      .iRA1(ra1), .oRD1(regReadData1),
      .iRA2(ra2), .oRD2(regReadData2));
   assign regWriteData = aluOut; /*-目前仅支持将ALU运算结果写入寄存器堆，
                                    TODO：增加Load类指令时需修改 -*/

   // ALU
   logic [31:0] aluOut;
   ALU alu(
       .iX(regReadData1),
       .iY(immData),
       .iALUop(aluOp),
       .oF(aluOut),
       .moveBit(ra2)
   );

   /*-TODO 连接数据存储器 -*/


//---------------------- 送给调试器的变量 ------------------------//

    //送给调试器的观察信号，需要与虚拟面板的信号框相对应
    struct packed{
        /*-TODO 在这里添加观察信号的类型 -*/
        logic [3:0] ALUop;            //对应虚拟元件WS2
        logic RegWrite;               //对应虚拟元件WS1
        logic [4:0] ImmType;          //对应虚拟元件WS0
    }ws;
    always_comb begin
        /*-【注意】添加观察信号类型后须关联相应变量！-*/
        ws.ALUop = aluOp;             //对应虚拟元件WS2
        ws.RegWrite = cRegWrite;      //对应虚拟元件WS1
        ws.ImmType = cImm_type;       //对应虚拟元件WS0
    end

    //送给调试器的观察变量，需要与虚拟面板的数据框相对应
    struct packed{
        /*-TODO 在这里添加观察数据的类型 -*/
        logic [3:0] ALUop;
        logic [31:0] aluOut;       //对应虚拟元件WD8
        logic [31:0] immData;      //对应虚拟元件WD7
        logic [31:0] regReadData1; //对应虚拟元件WD6
        logic [4:0]  ra2;          //对应虚拟元件WD5，5位
        logic [4:0]  ra1;          //对应虚拟元件WD4，5位
        logic [4:0]  wa;           //对应虚拟元件WD3，5位
        logic [31:0] instruction;  //对应虚拟元件WD2
        logic [31:0] pc;           //对应虚拟元件WD1
        logic [31:0] nextPC;       //对应虚拟元件WD0
    }wd;
    always_comb begin
        /*-【注意】添加观察数据类型后须关联相应变量！-*/
        wd.ALUop        = aluOp;
        wd.aluOut       = aluOut;       //对应虚拟元件WD8
        wd.immData      = immData;      //对应虚拟元件WD7
        wd.regReadData1 = regReadData1; //对应虚拟元件WD6
        wd.ra2          = ra2;          //对应虚拟元件WD5，5位
        wd.ra1          = ra1;          //对应虚拟元件WD4，5位
        wd.wa           = wa;           //对应虚拟元件WD3，5位
        wd.instruction  = instruction;  //对应虚拟元件WD2
        wd.pc           = pc;           //对应虚拟元件WD1
        wd.nextPC       = nextPC;       //对应虚拟元件WD0
    end

    // 调试器部分，请勿修改！
    WatchChain #(.DATAWIDTH($bits(ws)+$bits(wd))) WatchChain_inst(
        .DataIn({ws,wd}),
        .ScanIn(iScanIn),
        .ScanOut(oScanOut),
        .ShiftDR(iScanCtrl[1]),
        .CaptureDR(iScanCtrl[0]),
        .TCK(iScanClk)
    );
    assign oCurrent_PC = pc;
    assign oFetch = 1'b1;

endmodule


// --------------------------------------------------------------------
// Controller模块
// --------------------------------------------------------------------

module Controller(
   input  logic [6:0] iOpcode,
   input  logic [2:0] iFunct3,
   input  logic [6:0] iFunct7,
   /*- TODO：扩充指令时在这里增加端口 -*/
   output logic [3:0] oALUop,
   output logic oRegWrite,
   output logic [4:0] oImm_type   //对应五种类型：{J,U,B,S,I}
);

always @ * begin
   /*- TODO：扩充指令时需修改 ...... -*/

   //I型指令
   if (iOpcode==7'b0010011) begin
      oImm_type = 5'b00001;
      oRegWrite = 1'b1;
      if(iFunct3 == 3'b000) oALUop = 4'b0001;
      else if(iFunct3 == 3'b001) oALUop = 4'b0111;
      else if(iFunct3 == 3'b100) oALUop = 4'b0101;
      else if(iFunct3 == 3'b101 && iFunct7[5] == 1'b0) oALUop = 4'b1000;
      else if(iFunct3 == 3'b101 && iFunct7[5] == 1'b1) oALUop = 4'b0110;
      else if(iFunct3 == 3'b110) oALUop = 4'b0100;
      else if(iFunct3 == 3'b111) oALUop = 4'b0011;
   end
   else begin
      oALUop = 5'b00000;
      oImm_type = 5'b00000;
      oRegWrite = 1'b0;
   end
end
endmodule


// --------------------------------------------------------------------
// 立即数生成模块
// --------------------------------------------------------------------
module ImmGen( //立即数生成
   input  logic [4:0]  iImm_type,   //{J,U,B,S,I}
   input  logic [31:7] iInstruction,
   output logic [31:0] oImmediate
);
/*- TODO：增加其他类型的立即数需修改。目前只有I型，所以并未区分Imm_type -*/
always_comb begin
    if(iImm_type == 5'b00001)
        oImmediate = {{20{iInstruction[31]}}, iInstruction[31:20]};
    else if(iImm_type == 5'b00000)
        oImmediate = {32{1'b0}};
    else
        oImmediate = {32{1'bx}};
end
endmodule


// --------------------------------------------------------------------
// ALU模块
// --------------------------------------------------------------------
module ALU
#(parameter N=32)
(
   input logic [N-1:0] iX, iY,
   input logic [3:0] iALUop,
   input logic [4:0] moveBit,
   output logic [N-1:0] oF
);
wire [N-1:0] X = iX;
wire [N-1:0] Y = iY;
always_comb begin
   case (iALUop)
      4'b0001: oF = X + Y;
      4'b0010: oF = X - Y;
      4'b0011: oF = X & Y;
      4'b0100: oF = X | Y;
	  4'b0101: oF = X ^ Y;
	  4'b0110: oF = $signed(X) >>> moveBit;
	  4'b0111: oF = X << moveBit;
	  4'b1000: oF = X >> moveBit;
      default: oF = {4{1'bx}};
   endcase
end
endmodule


// --------------------------------------------------------------------
// 三端口寄存器堆模块
// --------------------------------------------------------------------
module RegisterFile
 #(
     parameter DATAWIDTH = 32,
     parameter ADDRWIDTH = 5
 )
(
	input  logic  Clk,
	input  logic  iWE,
	input  logic  [4:0] iWA, iRA1, iRA2,
    input  logic  [31:0] iWD,
    output logic  [31:0] oRD1, oRD2
);
/*- TODO：...  -*/
localparam MEMDEPTH = 1<<ADDRWIDTH;
logic [DATAWIDTH-1:0] mem[0:MEMDEPTH-1];

always_ff @(posedge Clk)
begin
    if(iWE)
        if(iWA!={ADDRWIDTH{1'b0}})
            mem[iWA] <= iWD;
end

assign oRD1 = mem[iRA1];
assign oRD2 = mem[iRA2];
endmodule


// --------------------------------------------------------------------
// DataReg模块
// --------------------------------------------------------------------
module DataReg
#(parameter N = 4)
(   output reg [N-1:0] oQ,
    input wire [N-1:0] iD,
    input wire Clk,
    input wire Load,
    input wire Reset
);
always @(posedge Clk or posedge Reset)
begin
  if (Reset)
		oQ <= 0;
  else if (Load)
		oQ <= iD;
end
endmodule