一、设计任务及要求：
设计任务：用Verilog HDL对CPLD芯片EPM240T100C5进行编程，并增加适当的电子元件，设计一个数字电子时钟电路
要求：
1．具有“时”“分”的数字显示功能，并可以进行时间校准
2．用发光二极管设计一个“表盘”，通过对应发光二极管的依次点亮来模拟表盘显示时间。
1 设计目的
1.进一步掌握数字电子技术的理论知识，培养工程设计能力和综合分析问题、解决问题的能力；
2.基本掌握常用电子电路的一般设计方法，提高电子电路的设计分析和实验能力；
3.掌握复杂可编程逻辑器件CPLD的原理及使用方法；
4.掌握Verilog HDL硬件描述语言的一般语法规则，学会设计方针CPLD器件，了解CPLD的烧写过程；
5.熟悉并学会选用电子元器件，为以后从事科研和生产工作打下一定的基础。
2 设计思路
2.1电路总体设计方案
2.2震荡电路
2.3控制电路
1.复位信号：系统初始化，并给时钟一个初始值， 零时零分零秒
2.时校准控制信号：校准小时计数
3.分校准控制信号：校准分钟计数
4.12/24小时计数切换控制信号
2.4时分秒计数器
1.秒计数器对秒脉冲计数，当计数至60时清零并产生分钟计数脉冲
2.分钟计数器对分钟计数脉冲计数，当计数至60时清零并产生小时计数脉冲。在分钟校准信号有效时对秒脉冲计数以实现分钟校时
3.小时计数器对小时计数脉冲计数，同时计数至12或24时清零。在小时校准信号有效时对秒脉冲进行计数以实现小时校时
4.设计过程 （每一个功能设计都要.包含源程序代码、编译结果、功能仿真波形结果）
4.1时分动态显示位码产生程序：编写一个2—4译码器，要求输出高电平有效。
源程序代码：
module dec_wei (
input [1:0]A,
output reg [3:0]W
);
always @(A)
W<=4'b0001<<(A);
Endmodule
4.2编写一个60进制秒计数器程序，对输入的秒脉冲进行计数。
源程序代码：
module dec_wei(SP,S);
input SP;
output reg[5:0]S;
always @(posedge SP)
if(S!=6'd59) S=S+6'd1;
else S=6'd0;
endmodule
4.3编写一个60进制分钟计数器程序，对输入的分钟脉冲进行计数。
实验代码：
module cnt60m(MP,Mh,Ml);
input MP;
output reg[2:0]Mh;
output reg[3:0]Ml;
always @(posedge MP)
if(Ml==4'd9)
begin
Ml<=1'd0;
Mh<=Mh+3'd1;
if(Mh==3'd5)
Mh<=1'd0;
end
else if(Ml!=4'd9) begin
Ml<=Ml+1'd1;
end
endmodule
4.4编写一个12进制的小时计数器，对输入的小时脉冲进行计数。
实验代码：
module cnt12h (HP,Hl,Hh);
input HP;
output reg[3:0]Hl;
output reg[1:0]Hh;
always @(posedge HP)
if({Hh,Hl}==6'h11)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd1;
Hh<=Hh+2'd1;
end
endmodule
4.5编写一个24进制的小时计数器，对输入的小时脉冲进行计数。
实验代码：
module cnt24h (HP,Hl,Hh);
input HP;
output reg[3:0]Hl;
output reg[1:0]Hh;
always @(posedge HP)
if({Hh,Hl}==6'h23)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd1;
Hh<=Hh+4'd1;
end
endmodule
3.6编写一个12/24进制小时计数器程序，对输入的脉冲进行计数。当输入控制信号Hc=1时是24进制，否则12进制。
实验代码：
module cnt12_24 (HP,Hl,Hh,Hc);
input HP;
input Hc;
output reg[3:0]Hl;
output reg[1:0]Hh;
always @(posedge HP)
if(Hc==1'd1)
begin
if({Hh,Hl}==6'h23)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+4'd1;
end
end
else
begin
if({Hh,Hl}==6'h11)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
endmodule
4.6编写一个时分秒计数器程序，对输入的秒脉冲进行计数。并且当输入控制信号Hc=1时是24进制，否则12进制。
实验代码：
module cnt_smh (Clk,Hc,Hh,Hl,Mh,Ml,S);
input Clk,Hc;
output reg[3:0]Hl;
output reg[1:0]Hh;
output reg[2:0]Mh;
output reg[3:0]Ml;
output reg[5:0]S;
always @(posedge Clk)
if(S!=6'd59)
//begin//秒
S<=S+6'd1;
else
begin
S<=6'd0;
Ml<=Ml+1'd1;//秒进位分加1
if(Ml!=4'd9)
Ml<=Ml+1'd1;
else
begin
Ml<=1'd0;
Mh<=Mh+3'd1;
if(Mh==3'd5)
begin
Mh<=1'd0;
Hl<=Hl+4'd1;//分进位时加1
if(Hc==1'd1)//时
begin
if({Hh,Hl}==6'h23)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+4'd1;
end
end
else
begin
if({Hh,Hl}==6'h11)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
end
end
end
endmodule
4.7编写一个带控制功能的时分秒程序，对输入的秒脉冲进行计数。
控制信号 Hc=1时是24进制，否则12进制
Cm=1时分钟正常计数，否则分钟校时
Hm=1时小时正常计数，否则小时校时
RST=0时复位，所有计数器回到0
实验代码：
module cnt (Sp,RST,Ch,Cm,Hc,S,Ml,Mh,Hl,Hh);
input Sp,RST,Ch,Cm,Hc;//秒脉冲，复位，小时、分校准
output reg[3:0]Hl;
output reg[1:0]Hh;
output reg[2:0]Mh;
output reg[3:0]Ml;
output reg[5:0]S;
always @(posedge Sp)
if(RST==0)
begin
Hh<=2'd0;
Hl<=4'd0;
Mh<=3'd0;
Ml<=4'd0;
S<=6'd0;
end
else
begin
case({Cm,Ch})
2'b11:begin
if(S!=6'd59)
//begin//秒
S<=S+6'd1;
else
begin
S<=6'd0;
Ml<=Ml+1'd1;//秒进位分加1
if(Ml!=4'd9)
Ml<=Ml+1'd1;
else
begin
Ml<=1'd0;
Mh<=Mh+3'd1;
if(Mh==3'd5)
begin
Mh<=1'd0;
Hl<=Hl+4'd1;//分进位时加1
if(Hc==1'd1)//时
begin
if({Hh,Hl}==6'h23)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
else
begin
if({Hh,Hl}==6'h11)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
end
end
end
end
2'b10:begin
if(S!=6'd59)
//begin//秒
S<=S+6'd1;
else
begin
S<=6'd0;
if(Hc==1'd1)//时
begin
if({Hh,Hl}==6'h23)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
else
begin
if({Hh,Hl}==6'h11)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
end
end
2'b01:begin
if(S!=6'd59)
S<=S+6'd1;
else
begin
S<=6'd0;
Ml<=Ml+1'd1;//秒进位分加1
if(Ml!=4'd9)
Ml<=Ml+1'd1;
else
begin
Ml<=1'd0;
Mh<=Mh+3'd1;
if(Mh==3'd5)
begin
Mh<=1'd0;
Hl<=Hl+4'd1;//分进位时加1
end
end
end
end
2'b00:begin
if(S!=6'd59)
//begin//秒
S<=S+6'd1;
else
begin
S<=6'd0;
Ml<=Ml+1'd1;//秒进位分加1
if(Ml!=4'd9)
Ml<=Ml+1'd1;
else
begin
Ml<=1'd0;
Mh<=Mh+3'd1;
if(Mh==3'd5)
begin
Mh<=1'd0;
Hl<=Hl+4'd1;//分进位时加1
if(Hc==1'd1)//时
begin
if({Hh,Hl}==6'h23)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
else
begin
if({Hh,Hl}==6'h11)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
end
end
end
end
endcase
end
endmodule
4.8编写一个带控制功能的时分秒程序，对输入的秒脉冲进行计数。
控制信号 Hc=1时是24进制，否则12进制:
Cm=1时分钟正常计数，否则分钟校时
Hm=1时小时正常计数，否则小时校时
RST=0时复位，所有计数器回到0
再加上秒圆盘显示译码程序
实验代码：
module cnt (Sp,RST,Ch,Cm,Hc,S,Ml,Mh,Hl,Hh,Sh,Sl);
input Sp,RST,Ch,Cm,Hc;//秒脉冲，复位，小时、分校准
output reg[3:0]Hl;
output reg[1:0]Hh;
output reg[2:0]Mh;
output reg[3:0]Ml;
output reg[5:0]S;
output wire[7:0]Sh,Sl;
always @(posedge Sp)
if(RST==0)
begin
Hh<=2'd0;
Hl<=4'd0;
Mh<=3'd0;
Ml<=4'd0;
S<=6'd0;
end
else
begin
case({Cm,Ch})
2'b11:begin
if(S!=6'd59)
//begin//秒
S<=S+6'd1;
else
begin
S<=6'd0;
Ml<=Ml+1'd1;//秒进位分加1
if(Ml!=4'd9)
Ml<=Ml+1'd1;
else
begin
Ml<=1'd0;
Mh<=Mh+3'd1;
if(Mh==3'd5)
begin
Mh<=1'd0;
Hl<=Hl+4'd1;//分进位时加1
if(Hc==1'd1)//时
begin
if({Hh,Hl}==6'h23)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
else
begin
if({Hh,Hl}==6'h11)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
end
end
end
end
2'b10:begin
if(S!=6'd59)
//begin//秒
S<=S+6'd1;
else
begin
S<=6'd0;
if(Hc==1'd1)//时
begin
if({Hh,Hl}==6'h23)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
else
begin
if({Hh,Hl}==6'h11)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
end
end
2'b01:begin
if(S!=6'd59)
S<=S+6'd1;
else
begin
S<=6'd0;
Ml<=Ml+1'd1;//秒进位分加1
if(Ml!=4'd9)
Ml<=Ml+1'd1;
else
begin
Ml<=1'd0;
Mh<=Mh+3'd1;
if(Mh==3'd5)
begin
Mh<=1'd0;
Hl<=Hl+4'd1;//分进位时加1
end
end
end
end
2'b00:begin
if(S!=6'd59)
//begin//秒
S<=S+6'd1;
else
begin
S<=6'd0;
Ml<=Ml+1'd1;//秒进位分加1
if(Ml!=4'd9)
Ml<=Ml+1'd1;
else
begin
Ml<=1'd0;
Mh<=Mh+3'd1;
if(Mh==3'd5)
begin
Mh<=1'd0;
Hl<=Hl+4'd1;//分进位时加1
if(Hc==1'd1)//时
begin
if({Hh,Hl}==6'h23)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
else
begin
if({Hh,Hl}==6'h11)
{Hh,Hl}<=6'h0;
else
if(Hl!=4'd9)
Hl<=Hl+4'd1;
else
begin
Hl<=4'd0;
Hh<=Hh+2'd1;
end
end
end
end
end
end
endcase
end
assign Sh=(8'b00000001<<({S[5],S[4],S[3]}));
assign Sl=~(8'b00000001<<({S[2],S[1],S[0]}));
endmodule
4.9将前面的程序加上对32768Hz的震荡信号进行计数。（最终版）
实验代码：
module clk182(CP,RST,Hc,Ch,Cm,Sh,Sl,W,ddo,pin_50,pin_51);
input CP,RST,Ch,Cm,Hc,pin_50,pin_51;//秒脉冲，复位，小时、分校准
output wire[3:0]W;
output wire[7:0]Sh,Sl;
output wire[7:0]ddo;
//中间变量
reg[3:0]Hl;
reg[1:0]Hh;
reg[2:0]Mh;
reg[3:0]Ml;
reg[5:0]S;
reg[14:0]Q;
reg[6:0]Hhd,Hld,Mhd,Mld;
wire Sp;
wire[7:0]Hhdo,Hldo,Mhdo,Mldo;
always @(posedge CP)
begin
if(RST==1'd0)
begin
Hh<=2'd2;
Hl<=4'd3;
Mh<=3'd5;
Ml<=4'd9;
S<=6'd59;
end
else
begin
if(Q!=15'd32767)
Q<=Q+1'd1;
else
begin
Q<=1'd0;
case({Ch,Cm})
2'b11:
begin
if(S!=6'd59)
S<=S+1'd1;
else
begin
S<=1'd0;
if(Ml==4'd9)
begin
if(Mh!=3'd5)
begin
Mh<=Mh+1'd1;
Ml<=1'd0;
end
else
begin
Mh<=1'd0;
Ml<=1'd0;
if(Hc==1'd0)
begin
if(Hl==1'd1&&Hh==1'd1)
begin
Hl<=1'd0;
Hh<=1'd0;
end
else if(Hl==4'd9)
begin
Hl<=1'd0;
Hh<=Hh+1'd1;
end
else Hl<=Hl+1'd1;
end
else
begin
if(Hl==4'd9)
begin
Hl<=1'd0;
Hh<=Hh+1'd1;
end
else if(Hl==2'd3&&Hh==2'd2)
begin
Hh<=1'd0;
Hl<=1'd0;
end
else Hl<=Hl+1'd1;
end
end
end
else Ml<=Ml+1'd1;
end
end
2'b10:
begin
if(Ml!=4'd9)
Ml<=Ml+1'd1;
else
begin
if(Mh==3'd5)
begin
Ml<=1'd0;
Mh<=1'd0;
end
else
begin
Ml<=1'd0;
Mh<=Mh+1'd1;
end
end
end
2'b01:
begin
if(Hc==1'd0)
begin
if(Hl==1'd1&&Hh==1'd1)
begin
Hl<=1'd0;
Hh<=1'd0;
end
else if(Hl==4'd9)
begin
Hl<=1'd0;
Hh<=Hh+1'd1;
end
else Hl<=Hl+1'd1;
end
else
begin
if(Hl==4'd9)
begin
Hl<=1'd0;
Hh<=Hh+1'd1;
end
else if(Hl==2'd3&&Hh==2'd2)
begin
Hh<=1'd0;
Hl<=1'd0;
end
else Hl<=Hl+1'd1;
end
end
2'b00:
begin
if(S!=6'd59)
S<=S+1'd1;
else S<=1'd0;
if(Ml!=4'd9)
Ml<=Ml+1'd1;
else
begin
if(Mh==3'd5)
begin
Ml<=1'd0;
Mh<=1'd0;
end
else
begin
Ml<=1'd0;
Mh<=Mh+1'd1;
end
end
if(Hc==1'd0)
begin
if(Hl==1'd1&&Hh==1'd1)
begin
Hl<=1'd0;
Hh<=1'd0;
end
else if(Hl==4'd9)
begin
Hl<=1'd0;
Hh<=Hh+1'd1;
end
else Hl<=Hl+1'd1;
end
else
begin
if(Hl==4'd9)
begin
Hl<=1'd0;
Hh<=Hh+1'd1;
end
else if(Hl==2'd3&&Hh==2'd2)
begin
Hh<=1'd0;
Hl<=1'd0;
end
else Hl<=Hl+1'd1;
end
end
endcase
end
case (Ml)
4'b0000:Mld<=7'b0111111;
4'b0001:Mld<=7'b0000110;
4'b0010:Mld<=7'b1011011;
4'b0011:Mld<=7'b1001111;
4'b0100:Mld<=7'b1100110;
4'b0101:Mld<=7'b1101101;
4'b0110:Mld<=7'b1111101;
4'b0111:Mld<=7'b0000111;
4'b1000:Mld<=7'b1111111;
4'b1001:Mld<=7'b1101111;
endcase
case(Mh)
3'b000:Mhd<=7'b0111111;
3'b001:Mhd<=7'b0000110;
3'b010:Mhd<=7'b1011011;
3'b011:Mhd<=7'b1001111;
3'b100:Mhd<=7'b1100110;
3'b101:Mhd<=7'b1101101;
endcase
case(Hl)
4'b0000:Hld<=7'b0111111;
4'b0001:Hld<=7'b0000110;
4'b0010:Hld<=7'b1011011;
4'b0011:Hld<=7'b1001111;
4'b0100:Hld<=7'b1100110;
4'b0101:Hld<=7'b1101101;
4'b0110:Hld<=7'b1111101;
4'b0111:Hld<=7'b0000111;
4'b1000:Hld<=7'b1111111;
4'b1001:Hld<=7'b1101111;
endcase
case(Hh)
2'b00:Hhd<=7'b0111111;
2'b01:Hhd<=7'b0000110;
2'b10:Hhd<=7'b1011011;
endcase
end
end
assign ddo=Hhdo+Hldo+Mhdo+Mldo;
assign Hhdo={1'b0,Hhd}&{W[3],W[3],W[3],W[3],W[3],W[3],W[3],W[3]};
assign Hldo={Sp,Hld}&{W[2],W[2],W[2],W[2],W[2],W[2],W[2],W[2]};
assign Mhdo={1'b0,Mhd}&{W[1],W[1],W[1],W[1],W[1],W[1],W[1],W[1]};
assign Mldo={1'b0,Mld}&{W[0],W[0],W[0],W[0],W[0],W[0],W[0],W[0]};
assign W=(4'b0001<<({Q[9],Q[8]}));
assign Sh=(8'b00000001<<({S[5],S[4],S[3]}));
assign Sl=~(8'b00000001<<({S[2],S[1],S[0]}));
assign Sp=Q[14];
endmodule
#以上为本人浅写，仅供参考
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