八选一数据选择器

library ieee;
use ieee.std_logic_1164.all;

entity SH02 is
port(a:in std_logic_vector(7 downto 0);
     s:in std_logic_vector(2 downto 0);
	  y:out std_logic
     );
end SH02;

architecture a1 of SH02 is  
signal sel:integer ;
begin  
      with sel select  
        y <= a(0) when 0,  
                  a(1) when 1,  
                  a(2) when 2,  
                  a(3) when 3,  
                  a(4) when 4,  
                  a(5) when 5,  
                  a(6) when 6,  
                  a(7) when 7,  
                  'X' when others;  
          sel<=0 when s(0)='0' and s(1)='0' and s(2)='0' else
	          1 when s(0)='0' and s(1)='0' and s(2)='1' else
				2 when s(0)='0' and s(1)='1' and s(2)='0' else
				3 when s(0)='0' and s(1)='1' and s(2)='1' else
			   4 when s(0)='1' and s(1)='0' and s(2)='0' else
				5 when s(0)='1' and s(1)='0' and s(2)='1' else
				6 when s(0)='1' and s(1)='1' and s(2)='0' else
				7 when s(0)='1' and s(1)='1' and s(2)='1' else
				8;
end a1;