1.打开modesim软件新建工程,如下图:
2.选择文件夹新建工程:
3.添加代码:
module fulladd(sum,c_out,a,b,c_in);
output sum,c_out;
input a,b,c_in;
wire s1,c1,c2;
xor (s1,a,b);
and (c1,a,b);
xor (sum,s1,c_in);
and (c2,s1,c_in);
or (c_out,c2,c1;);
endmodule
楠木叶纶 19:46:59
module test;
wire sum, c_out;
reg a,b,c_in;
fulladd fadd(sun,c_out,a,b,c_in) ;
/*
initial
begin
#15 force fadd.sum=a&b&c_in;
#20 release fadd.sun;
#10 $stop;
end
*/
initial
begin
a=0;b=0;c_in=0;
#10 a=0;b=0;c_in=1;
#10 a=0;b=1;c_in=0;
#10 a=0;b=1;c_in=1;
#10 a-1;b=0;c_in=0;
#10 a=1;b=0;c_in=1;
#10 a=1;b=1;c_in=0;
#10 a=1;b=1;C_in=1;
#10 $stop;
end
endmodule
4.实验结果: