特权同学《Verilog边码边学》P7 课后习题答案

注意，我的是vlg_design1!

 

vlg_design1.v

`timescale 1ns/1ps
module vlg_design1(
	input clk,
	input rst_n,
	output reg sim_clk,
	output reg [3:0] count_num
    );
	reg [2:0] count;
	//先进行20分频
	always @(posedge clk) begin
		if(!rst_n) begin
		count<=3'd0;
		count_num<=4'd0;
		sim_clk<=1'b0;
		end	
		else if(count<3'd4) count <= count + 1'b1;
		else begin
			count <= 5'd0;
		end
	end
	always @(posedge clk) begin
		if(!rst_n) begin
			count_num<=1'b0;
			sim_clk<=1'b0;
		end
		else if(count==3'd4) begin
			sim_clk<=1'd1;
		end
		else sim_clk<=1'd0;
	end
	always @(negedge sim_clk) begin
		if(!rst_n) count_num<=1'd0;
		else if(count_num == 4'd15) count_num<=1'd0;
		else count_num <= count_num + 1'b1;	
	end

endmodule

testbench_top.v

`timescale 1ns/1ps
module testbench_top();
	

//参数定义

`define CLK_PERIORD		10		//时钟周期设置为10ns（100MHz）	


//接口申明
	
reg clk;
reg rst_n;
wire sim_clk;
wire [3:0] count_num;

	
//对被测试的设计进行例化
	
vlg_design1		uut_vlg_design1(
	.clk(clk),
	.rst_n(rst_n),
	.sim_clk(sim_clk),
	.count_num(count_num)
    );	
	

//复位和时钟产生

	//时钟和复位初始化、复位产生
initial begin
	clk <= 0;
	rst_n <= 0;
	#1000;
	rst_n <= 1;
end
	
	//时钟产生
always #(`CLK_PERIORD/2) clk = ~clk;	


//测试激励产生

initial begin
	@(posedge rst_n);	//等待复位完成
	repeat(10) begin
		@(posedge clk);
	end
	# 10_000;
	
	$stop;
end


endmodule