Pr flow learning(一)

一、init design

        1.Loading the design

在init 阶段主要做的工作就是读入一些设计文件,比如libraries, netlist, and timing environment,通常我们可以在log中看到int design读入的一些文件:

ItemsLog message 
Loading MMMC#% Begin Load MMMC data ... #% End Load MMMC data ...
Loading LEF file

Loading LEF file /pdk/TSMC12/xxx

Reading verilog netlistReading verilog netlist './input/xxx.v.gz
Reading power intend fileReading power intent file ./input/xxx.upf

2.review the init design

在init阶段需要进行如下的检查:

(1)检查lef与lib的一致性,在log里面报的Warning类型为ENCSYC-2.

(2)检查是否有blackbox,unless your design is being done using a blackbox style of floorplanning, there should be no blackboxes in the design,如果有的话会报Found empty module(bbox) 

(3)确认netlist唯一性,如果不唯一会报*** Netlist is NOT unique.

(4)确保buffers, inverters, and delay cells被正确定义。

(5)SDC 检查:检查waring或者error是否有报unaccept的约束,是否有pin,net,cell是not found;检查是否有Illegal endpoints

(6)确保Quantus techfile and LEF files match.

(7)确保抽RC的温度正确等。

二、Floorplanning and Initial Placement

1.Floorplan

在block设计中,顶层设计人员会对整个芯片做partion,block需要基于顶层的Def进行volage规划,macro摆放,io 摆放,电源规划,add physical cell,add welltap,add endcap等。

2.floorplan后需要确认项

floorplan做完之后需要确认power是否global上,blkg是否添加正确,具体检查项如下:

The power grid should be defined:

(1)Global net connections are property defined using the globalNetConnect command.

(2)Nets requiring optimization should be defined as signal (regular) nets.Optimizations treats nets in the SPECIALNETS as dont-touch.

(3)PINS marked with + SPECIAL cannot be optimized.

(4)FollowPin routing should align to rows/cells with the correct orientation (VDD pin to VDD followPin)

(5)Gaps between standard cells and blocks should be covered with soft or hard blockages.Placement cannot place cells in the area of soft blockages but optimization and CTS can.

(6)All blocks should be marked fixed.

(7)Tracks should match IO pins and placement grid(rows).

(8)Use add_tracks to update the tracks.

三、Placement

1.place_opt_design

innovus工具中做place的步骤集成在place_opt_design这个命令里,它所做的工作主要包括以下几个部分:

(1)place physical cell

(2)global place

(3)scan reorder

(4)detail place

(5)congestion repair

2.preCTS阶段常见的timing和congestion问题的优化策略

(1)如果某些net没有被optimized,使用report IgnoredNets -outfile fileName报出,检查为什么没有被优化

(2)如果timing在优化后变poor或degraded,检查log,可能与physical update placement legalization/earlyGlobalRouting有关,在这种情况下,检查routing congestion,scaling factors和initial placement

(3)使用set_dont_touch或set_dont_use_attribute,确保相应的Cell可以被优化,reportFootPrint -dontTouchNuse -outfile fileName

(4)如果相似路径没有被优化设置path group。

(5)如果critical paths经过了congested区域,尝试使用cell padding(同上),或partial placement blk减小cong;

(6)使用useful skew满足时序要求,同样useful skew可以使用setOptMode -usefulSkew false关掉;

(7)如果clock gating在critical path上检查,可以创建单独的path group并且over constrain them,但是over constraining会增加runtime;

(8)high routing cong可能主要来源于nets detouring,因此除了在fp和placement阶段,提前对weak cell设置dont_use,即setDontUse cellName(setDontUse和SDC中的set_dont_use的区别:setDontUse可以对所有的operating mode起作用,但是set_dont_use只影响operating mode to which it is applied)

(9)监控density increase,减小Setup或者drv的margin,设置setOptMode -setup TargetSlack -0.2比target是-0.5ns好,设置drv的命令:setOptMode -setupTargetSlack slack -drcMargin value

四、CTS

1.ccopt_design –cts

该命令是做cts阶段的主要命令,ccopt_design –cts执行之后工具的行为:

(1)Detail route clock nets using NanoRoute

(2)Switch timing clocks to propagated mode and update source latencies to maintain correct I/O and inter-clock timing.

(3)There is no need to use the update_io_latency command after the ccopt_design command and doing so will not give valid results.

2.Hold optimization

        cts之后可以让工具先优化一轮hold,也就是postcts,那么自己优化hold违例通常要考虑哪些呢,这里ug给出了一参考思路。

(1)确保hold timing uncertainty是真实的,太大的uncertainty会导致插入thousands more buffers;

(2)确保delay cell可以被使用,避免出现一些用于修hold的weak buffers,因为这种对于routing detour和signal integrity(信号完整性)很敏感;

(3)For multi-Vth design,ensure that you run leakage optimization(through optDesign or opt power)before running hold fixing since leakage reduction improves hold timing;

(4)在placement阶段添加cell padding预留fix hold的空间,但是cell padding必须在postCTS之前remove掉;

(5)Ensure that timing constraints are correctly in sync between setup and hold(especially multicycle paths)

(6)确保clock tree good;

(7)对于有很多条hold违例的路径,推荐在postCTS阶段run hold fixing,然后在postroute阶段修复剩余的hold违例。

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