应朋友请求写了一个纯VERILOG的LMX2594的配置。
首先写一个SPI的接口：
/*
lmx2594_spi_master lmx2594_spi_master (
.clk() ,
.rst(),
.W0R1(),
.pin_mosi(),
.pin_sclk(),
.pin_miso(),
.wr(),
.busy(),
.addr() ,
.din(),
.dout()
);
*/
module lmx2594_spi_master (
input clk,rst,W0R1,
output reg pin_mosi,pin_sclk,pin_csn,
input pin_miso,
input wr,
output busy,
input [6:0] addr ,
input [15:0] din,
output reg [15:0] dout
);
reg [3:0] d ; always @ (posedge clk) if (rst) d<=0; else d<=d+1;
wire move = d == 0;
reg [7:0] st ;
reg [23:0] reg24 ; always@(posedge clk) if (wr&st==10) reg24 <= {W0R1,addr[6:0],din[15:0]};
reg[23:0] result24; always@(posedge clk) if (st==148 ) dout <= result24[15:0] ;
reg pin_miso_r ; always@(posedge clk) pin_miso_r<= pin_miso;
always@(posedge clk) if (st==20)pin_csn<= 1'b0 ;else if ((st==149) ||(st==0)) pin_csn<= 1'b1 ;
always@(posedge clk) if (rst) st<=0; else case(st)
0 : begin st <= 10 ; pin_mosi<=0;pin_sclk<=0;end
10 : begin pin_mosi<=0;pin_sclk<=0; if ( wr ) st<=20 ;end
20 : if ( move ) st<=21 ;
21 : if ( move ) st<=100 ;
/*
main(){
int i ,j;for(i=j=0;i<24*2;){
printf("%d: begin pin_sclk<=0; pin_mosi<= reg24[%d] ; if (move) st<=st+1 ; end \n",100+i,(23-j));++i;
printf("%d: begin pin_sclk<=1; pin_mosi<= reg24[%d] ; result24[%d] <= pin_miso_r;if (move) st<=st+1 ; end \n\n",100+i,(23-j),(23-j)); j++; ++i;
}}
*/
100: begin pin_sclk<=0; pin_mosi<= reg24[23] ; if (move) st<=st+1 ; end
101: begin pin_sclk<=1; pin_mosi<= reg24[23] ; result24[23] <= pin_miso_r;if (move) st<=st+1 ; end
102: begin pin_sclk<=0; pin_mosi<= reg24[22] ; if (move) st<=st+1 ; end
103: begin pin_sclk<=1; pin_mosi<= reg24[22] ; result24[22] <= pin_miso_r;if (move) st<=st+1 ; end
104: begin pin_sclk<=0; pin_mosi<= reg24[21] ; if (move) st<=st+1 ; end
105: begin pin_sclk<=1; pin_mosi<= reg24[21] ; result24[21] <= pin_miso_r;if (move) st<=st+1 ; end
106: begin pin_sclk<=0; pin_mosi<= reg24[20] ; if (move) st<=st+1 ; end
107: begin pin_sclk<=1; pin_mosi<= reg24[20] ; result24[20] <= pin_miso_r;if (move) st<=st+1 ; end
108: begin pin_sclk<=0; pin_mosi<= reg24[19] ; if (move) st<=st+1 ; end
109: begin pin_sclk<=1; pin_mosi<= reg24[19] ; result24[19] <= pin_miso_r;if (move) st<=st+1 ; end
110: begin pin_sclk<=0; pin_mosi<= reg24[18] ; if (move) st<=st+1 ; end
111: begin pin_sclk<=1; pin_mosi<= reg24[18] ; result24[18] <= pin_miso_r;if (move) st<=st+1 ; end
112: begin pin_sclk<=0; pin_mosi<= reg24[17] ; if (move) st<=st+1 ; end
113: begin pin_sclk<=1; pin_mosi<= reg24[17] ; result24[17] <= pin_miso_r;if (move) st<=st+1 ; end
114: begin pin_sclk<=0; pin_mosi<= reg24[16] ; if (move) st<=st+1 ; end
115: begin pin_sclk<=1; pin_mosi<= reg24[16] ; result24[16] <= pin_miso_r;if (move) st<=st+1 ; end
116: begin pin_sclk<=0; pin_mosi<= reg24[15] ; if (move) st<=st+1 ; end
117: begin pin_sclk<=1; pin_mosi<= reg24[15] ; result24[15] <= pin_miso_r;if (move) st<=st+1 ; end
118: begin pin_sclk<=0; pin_mosi<= reg24[14] ; if (move) st<=st+1 ; end
119: begin pin_sclk<=1; pin_mosi<= reg24[14] ; result24[14] <= pin_miso_r;if (move) st<=st+1 ; end
120: begin pin_sclk<=0; pin_mosi<= reg24[13] ; if (move) st<=st+1 ; end
121: begin pin_sclk<=1; pin_mosi<= reg24[13] ; result24[13] <= pin_miso_r;if (move) st<=st+1 ; end
122: begin pin_sclk<=0; pin_mosi<= reg24[12] ; if (move) st<=st+1 ; end
123: begin pin_sclk<=1; pin_mosi<= reg24[12] ; result24[12] <= pin_miso_r;if (move) st<=st+1 ; end
124: begin pin_sclk<=0; pin_mosi<= reg24[11] ; if (move) st<=st+1 ; end
125: begin pin_sclk<=1; pin_mosi<= reg24[11] ; result24[11] <= pin_miso_r;if (move) st<=st+1 ; end
126: begin pin_sclk<=0; pin_mosi<= reg24[10] ; if (move) st<=st+1 ; end
127: begin pin_sclk<=1; pin_mosi<= reg24[10] ; result24[10] <= pin_miso_r;if (move) st<=st+1 ; end
128: begin pin_sclk<=0; pin_mosi<= reg24[9] ; if (move) st<=st+1 ; end
129: begin pin_sclk<=1; pin_mosi<= reg24[9] ; result24[9] <= pin_miso_r;if (move) st<=st+1 ; end
130: begin pin_sclk<=0; pin_mosi<= reg24[8] ; if (move) st<=st+1 ; end
131: begin pin_sclk<=1; pin_mosi<= reg24[8] ; result24[8] <= pin_miso_r;if (move) st<=st+1 ; end
132: begin pin_sclk<=0; pin_mosi<= reg24[7] ; if (move) st<=st+1 ; end
133: begin pin_sclk<=1; pin_mosi<= reg24[7] ; result24[7] <= pin_miso_r;if (move) st<=st+1 ; end
134: begin pin_sclk<=0; pin_mosi<= reg24[6] ; if (move) st<=st+1 ; end
135: begin pin_sclk<=1; pin_mosi<= reg24[6] ; result24[6] <= pin_miso_r;if (move) st<=st+1 ; end
136: begin pin_sclk<=0; pin_mosi<= reg24[5] ; if (move) st<=st+1 ; end
137: begin pin_sclk<=1; pin_mosi<= reg24[5] ; result24[5] <= pin_miso_r;if (move) st<=st+1 ; end
138: begin pin_sclk<=0; pin_mosi<= reg24[4] ; if (move) st<=st+1 ; end
139: begin pin_sclk<=1; pin_mosi<= reg24[4] ; result24[4] <= pin_miso_r;if (move) st<=st+1 ; end
140: begin pin_sclk<=0; pin_mosi<= reg24[3] ; if (move) st<=st+1 ; end
141: begin pin_sclk<=1; pin_mosi<= reg24[3] ; result24[3] <= pin_miso_r;if (move) st<=st+1 ; end
142: begin pin_sclk<=0; pin_mosi<= reg24[2] ; if (move) st<=st+1 ; end
143: begin pin_sclk<=1; pin_mosi<= reg24[2] ; result24[2] <= pin_miso_r;if (move) st<=st+1 ; end
144: begin pin_sclk<=0; pin_mosi<= reg24[1] ; if (move) st<=st+1 ; end
145: begin pin_sclk<=1; pin_mosi<= reg24[1] ; result24[1] <= pin_miso_r;if (move) st<=st+1 ; end
146: begin pin_sclk<=0; pin_mosi<= reg24[0] ; if (move) st<=st+1 ; end
147: begin pin_sclk<=1; pin_mosi<= reg24[0] ; result24[0] <= pin_miso_r;if (move) st<=st+1 ; end
148: begin pin_sclk<=0; if (move) st<=st+1;end
149: begin pin_sclk<=0; if (move) st<=st+1;end
150: begin pin_sclk<=0; if (move) st<=st+1;end
151: begin if (move) st<=10; end
default st<=0;
endcase
assign busy = (wr==1) || (st!=10) ;
endmodule
之后写一个数组保存配置信息：
/*
cfg_rom cfg_rom(
.clk(),
.rst(),
.clr(),
.read(),
.dout(),
.last()
);
*/
module cfg_rom(
input clk,rst,clr,read,
output [23:0] dout,
output last
);
reg [7:0]cntr ;
always@(posedge clk)if (rst|clr) cntr<=0; else if (read) cntr<=cntr+1;
assign last = cntr == 45;
always@(posedge clk)
case (cntr)
/*
unsigned int info[]={
0x460000,
0x450000,
0x440089,
0x400077,
0x3E0000,
0x3D0001,
0x3B0000,
0x3003FC,
0x2F08CF,
0x2E0F23,
0x2D0320,
0x2C0000,
0x2B0000,
0x2A0000,
0x2903E8,
0x280000,
0x278204,
0x260198,
0x254000,
0x240841,
0x23119B,
0x22C3EA,
0x212A0A,
0x20210A,
0x1F0401,
0x1E0034,
0x1D0084,
0x1C2924,
0x190000,
0x180509,
0x178842,
0x162300,
0x14012C,
0x130965,
0x0E018C,
0x0D4000,
0x0C7001,
0x0B0018,
0x0A10D8,
0x090302,
0x081084,
0x0728B2,
0x041943,
0x020500,
0x010808,
0x00221C,
0xffffff //ending flag
};
main(){
int i ,j;
for(i=0;i<100;++i)
{
if(info[i]==0xffffff) break;
printf("%2d:dout<=24'h%06x;\n",i,info[i]);
}
}
*/
0:dout<=24'h460000;
1:dout<=24'h450000;
2:dout<=24'h440089;
3:dout<=24'h400077;
4:dout<=24'h3e0000;
5:dout<=24'h3d0001;
6:dout<=24'h3b0000;
7:dout<=24'h3003fc;
8:dout<=24'h2f08cf;
9:dout<=24'h2e0f23;
10:dout<=24'h2d0320;
11:dout<=24'h2c0000;
12:dout<=24'h2b0000;
13:dout<=24'h2a0000;
14:dout<=24'h2903e8;
15:dout<=24'h280000;
16:dout<=24'h278204;
17:dout<=24'h260198;
18:dout<=24'h254000;
19:dout<=24'h240841;
20:dout<=24'h23119b;
21:dout<=24'h22c3ea;
22:dout<=24'h212a0a;
23:dout<=24'h20210a;
24:dout<=24'h1f0401;
25:dout<=24'h1e0034;
26:dout<=24'h1d0084;
27:dout<=24'h1c2924;
28:dout<=24'h190000;
29:dout<=24'h180509;
30:dout<=24'h178842;
31:dout<=24'h162300;
32:dout<=24'h14012c;
33:dout<=24'h130965;
34:dout<=24'h0e018c;
35:dout<=24'h0d4000;
36:dout<=24'h0c7001;
37:dout<=24'h0b0018;
38:dout<=24'h0a10d8;
39:dout<=24'h090302;
40:dout<=24'h081084;
41:dout<=24'h0728b2;
42:dout<=24'h041943;
43:dout<=24'h020500;
44:dout<=24'h010808;
45:dout<=24'h00221c;
default dout <= 0 ;
endcase
endmodule
最后写一个顶层调用模块：
/*
lmx2594_master lmx2594_master (
.clk(),
.rst(),
.pin_mosi(),
.pin_sclk(),
.pin_miso(),
.done()
);
*/
module lmx2594_master (
input clk,rst,
output pin_mosi,pin_sclk,pin_csn,
input pin_miso,
output reg done
);
wire [23:0] info24 ;
wire last ,busy ;
reg read = 0 ;
reg clr = 0 ;
reg wr = 0 ;
reg [7:0] st ;
reg [31:0]d ;
always @(posedge clk) case (st )
10,32,40:d<=d+1;
default d<=0;
endcase
always@(posedge clk)clr <= st==2 ;
always@(posedge clk)read <= wr ;
always@(posedge clk)wr <= st==31 ;
always@(posedge clk) if (rst) st<=0; else
0: st <=1;
1:if (d==100*1000) st<=2;//por time
2:st<=10;
10: if (last) st<=100;else st<=20;
20: st<=30; //
30: st<=31;
31: st<=32; // do wr
32: if (d==10) st<=33;
33: if (busy==0) st<=40;
40: if (d==1000*100) st<=50;
50: st<=10;
100:st<=100;
default st<=0;
endcase
always@(posedge clk) done <= st==100;
cfg_rom cfg_rom(
.clk(clk),
.rst(rst),
.clr(clr),
.read(read),
.dout(info24),
.last(last )
);
lmx2594_spi_master lmx2594_spi_master (
.clk(clk) ,
.rst(rst),
.W0R1(1'b0),
.pin_mosi(pin_mosi),
.pin_sclk(pin_sclk),
.pin_miso(pin_miso),
.pin_csn(pin_csn),
.wr(wr),
.busy(busy),
.addr(info24[ 16+6 : 16 ] ) ,
.din(info24[15:0]),
.dout()
);
endmodule
最好仿真一下，写一下仿真测试文件：
module tb ;
reg clk=0,rst=0;
wire pin_mosi,pin_sclk,pin_miso,pin_csn,done ;
assign pin_miso =1'b1;
always #5 clk = ~clk ;
initial begin
rst = 1;
@(posedge clk);
@(posedge clk);
rst = 0;
end
initial begin
$dumpfile("vcd.vcd");
$dumpvars(0,tb);
end
lmx2594_master lmx2594_master (
.clk(clk),
.rst(rst),
.pin_mosi(pin_mosi),
.pin_sclk(pin_sclk),
.pin_miso(pin_miso),
.pin_csn(pin_csn)
.done(done)
);
endmodule
========================================================================
下面的代码是顺便写的CDCM6208驱动：
module CDCM6208_spi_master (
input clk,rst,W0R1,
output reg pin_mosi,pin_sclk,pin_csn,
input pin_miso,
input wr,
output busy,
input [15:0] addr ,
input [15:0] din,
output reg [15:0] dout
);
reg [3:0] d ; always @ (posedge clk) if (rst) d<=0; else d<=d+1;
wire move = d == 0;
reg [7:0] st ;
reg [23:0] reg32 ; always@(posedge clk) if (wr&st==10) reg32 <= {addr[15:0],din[15:0]};
reg[23:0] result32; always@(posedge clk) if (st==200 ) dout <= result32[15:0] ;
reg pin_miso_r ; always@(posedge clk) pin_miso_r<= pin_miso;
always@(posedge clk) if (st==20)pin_csn<= 1'b0 ;else if ((st==202) ||(st==0)) pin_csn<= 1'b1 ;
always@(posedge clk) if (rst) st<=0; else case(st)
0 : begin st <= 10 ; pin_mosi<=0;pin_sclk<=0;end
10 : begin pin_mosi<=0;pin_sclk<=0; if ( wr ) st<=20 ;end
20 : if ( move ) st<=21 ;
21 : if ( move ) st<=100 ;
100: begin pin_sclk<=0; pin_mosi<= reg32[31] ; if (move) st<=st+1 ; end
101: begin pin_sclk<=1; pin_mosi<= reg32[31] ; result32[31] <= pin_miso_r;if (move) st<=st+1 ; end
102: begin pin_sclk<=0; pin_mosi<= reg32[30] ; if (move) st<=st+1 ; end
103: begin pin_sclk<=1; pin_mosi<= reg32[30] ; result32[30] <= pin_miso_r;if (move) st<=st+1 ; end
104: begin pin_sclk<=0; pin_mosi<= reg32[29] ; if (move) st<=st+1 ; end
105: begin pin_sclk<=1; pin_mosi<= reg32[29] ; result32[29] <= pin_miso_r;if (move) st<=st+1 ; end
106: begin pin_sclk<=0; pin_mosi<= reg32[28] ; if (move) st<=st+1 ; end
107: begin pin_sclk<=1; pin_mosi<= reg32[28] ; result32[28] <= pin_miso_r;if (move) st<=st+1 ; end
108: begin pin_sclk<=0; pin_mosi<= reg32[27] ; if (move) st<=st+1 ; end
109: begin pin_sclk<=1; pin_mosi<= reg32[27] ; result32[27] <= pin_miso_r;if (move) st<=st+1 ; end
110: begin pin_sclk<=0; pin_mosi<= reg32[26] ; if (move) st<=st+1 ; end
111: begin pin_sclk<=1; pin_mosi<= reg32[26] ; result32[26] <= pin_miso_r;if (move) st<=st+1 ; end
112: begin pin_sclk<=0; pin_mosi<= reg32[25] ; if (move) st<=st+1 ; end
113: begin pin_sclk<=1; pin_mosi<= reg32[25] ; result32[25] <= pin_miso_r;if (move) st<=st+1 ; end
114: begin pin_sclk<=0; pin_mosi<= reg32[24] ; if (move) st<=st+1 ; end
115: begin pin_sclk<=1; pin_mosi<= reg32[24] ; result32[24] <= pin_miso_r;if (move) st<=st+1 ; end
116: begin pin_sclk<=0; pin_mosi<= reg32[23] ; if (move) st<=st+1 ; end
117: begin pin_sclk<=1; pin_mosi<= reg32[23] ; result32[23] <= pin_miso_r;if (move) st<=st+1 ; end
118: begin pin_sclk<=0; pin_mosi<= reg32[22] ; if (move) st<=st+1 ; end
119: begin pin_sclk<=1; pin_mosi<= reg32[22] ; result32[22] <= pin_miso_r;if (move) st<=st+1 ; end
120: begin pin_sclk<=0; pin_mosi<= reg32[21] ; if (move) st<=st+1 ; end
121: begin pin_sclk<=1; pin_mosi<= reg32[21] ; result32[21] <= pin_miso_r;if (move) st<=st+1 ; end
122: begin pin_sclk<=0; pin_mosi<= reg32[20] ; if (move) st<=st+1 ; end
123: begin pin_sclk<=1; pin_mosi<= reg32[20] ; result32[20] <= pin_miso_r;if (move) st<=st+1 ; end
124: begin pin_sclk<=0; pin_mosi<= reg32[19] ; if (move) st<=st+1 ; end
125: begin pin_sclk<=1; pin_mosi<= reg32[19] ; result32[19] <= pin_miso_r;if (move) st<=st+1 ; end
126: begin pin_sclk<=0; pin_mosi<= reg32[18] ; if (move) st<=st+1 ; end
127: begin pin_sclk<=1; pin_mosi<= reg32[18] ; result32[18] <= pin_miso_r;if (move) st<=st+1 ; end
128: begin pin_sclk<=0; pin_mosi<= reg32[17] ; if (move) st<=st+1 ; end
129: begin pin_sclk<=1; pin_mosi<= reg32[17] ; result32[17] <= pin_miso_r;if (move) st<=st+1 ; end
130: begin pin_sclk<=0; pin_mosi<= reg32[16] ; if (move) st<=st+1 ; end
131: begin pin_sclk<=1; pin_mosi<= reg32[16] ; result32[16] <= pin_miso_r;if (move) st<=st+1 ; end
132: begin pin_sclk<=0; pin_mosi<= reg32[15] ; if (move) st<=st+1 ; end
133: begin pin_sclk<=1; pin_mosi<= reg32[15] ; result32[15] <= pin_miso_r;if (move) st<=st+1 ; end
134: begin pin_sclk<=0; pin_mosi<= reg32[14] ; if (move) st<=st+1 ; end
135: begin pin_sclk<=1; pin_mosi<= reg32[14] ; result32[14] <= pin_miso_r;if (move) st<=st+1 ; end
136: begin pin_sclk<=0; pin_mosi<= reg32[13] ; if (move) st<=st+1 ; end
137: begin pin_sclk<=1; pin_mosi<= reg32[13] ; result32[13] <= pin_miso_r;if (move) st<=st+1 ; end
138: begin pin_sclk<=0; pin_mosi<= reg32[12] ; if (move) st<=st+1 ; end
139: begin pin_sclk<=1; pin_mosi<= reg32[12] ; result32[12] <= pin_miso_r;if (move) st<=st+1 ; end
140: begin pin_sclk<=0; pin_mosi<= reg32[11] ; if (move) st<=st+1 ; end
141: begin pin_sclk<=1; pin_mosi<= reg32[11] ; result32[11] <= pin_miso_r;if (move) st<=st+1 ; end
142: begin pin_sclk<=0; pin_mosi<= reg32[10] ; if (move) st<=st+1 ; end
143: begin pin_sclk<=1; pin_mosi<= reg32[10] ; result32[10] <= pin_miso_r;if (move) st<=st+1 ; end
144: begin pin_sclk<=0; pin_mosi<= reg32[9] ; if (move) st<=st+1 ; end
145: begin pin_sclk<=1; pin_mosi<= reg32[9] ; result32[9] <= pin_miso_r;if (move) st<=st+1 ; end
146: begin pin_sclk<=0; pin_mosi<= reg32[8] ; if (move) st<=st+1 ; end
147: begin pin_sclk<=1; pin_mosi<= reg32[8] ; result32[8] <= pin_miso_r;if (move) st<=st+1 ; end
148: begin pin_sclk<=0; pin_mosi<= reg32[7] ; if (move) st<=st+1 ; end
149: begin pin_sclk<=1; pin_mosi<= reg32[7] ; result32[7] <= pin_miso_r;if (move) st<=st+1 ; end
150: begin pin_sclk<=0; pin_mosi<= reg32[6] ; if (move) st<=st+1 ; end
151: begin pin_sclk<=1; pin_mosi<= reg32[6] ; result32[6] <= pin_miso_r;if (move) st<=st+1 ; end
152: begin pin_sclk<=0; pin_mosi<= reg32[5] ; if (move) st<=st+1 ; end
153: begin pin_sclk<=1; pin_mosi<= reg32[5] ; result32[5] <= pin_miso_r;if (move) st<=st+1 ; end
154: begin pin_sclk<=0; pin_mosi<= reg32[4] ; if (move) st<=st+1 ; end
155: begin pin_sclk<=1; pin_mosi<= reg32[4] ; result32[4] <= pin_miso_r;if (move) st<=st+1 ; end
156: begin pin_sclk<=0; pin_mosi<= reg32[3] ; if (move) st<=st+1 ; end
157: begin pin_sclk<=1; pin_mosi<= reg32[3] ; result32[3] <= pin_miso_r;if (move) st<=st+1 ; end
158: begin pin_sclk<=0; pin_mosi<= reg32[2] ; if (move) st<=st+1 ; end
159: begin pin_sclk<=1; pin_mosi<= reg32[2] ; result32[2] <= pin_miso_r;if (move) st<=st+1 ; end
160: begin pin_sclk<=0; pin_mosi<= reg32[1] ; if (move) st<=st+1 ; end
161: begin pin_sclk<=1; pin_mosi<= reg32[1] ; result32[1] <= pin_miso_r;if (move) st<=st+1 ; end
162: begin pin_sclk<=0; pin_mosi<= reg32[0] ; if (move) st<=st+1 ; end
163: begin pin_sclk<=1; pin_mosi<= reg32[0] ; result32[0] <= pin_miso_r;if (move) st<=200 ; end
200: begin pin_sclk<=0; if (move) st<=st+1;end
201: begin pin_sclk<=0; if (move) st<=st+1;end
202: begin pin_sclk<=0; if (move) st<=st+1;end
203: begin if (move) st<=10; end
default st<=0;
endcase
assign busy = (wr==1) || (st!=10) ;
endmodule
下面是顺便写的lmx2582的驱动。
/*
lmx2582_spi_master lmx2582_spi_master (
.clk() ,
.rst(),
.W0R1(),
.pin_mosi(),
.pin_sclk(),
.pin_miso(),
.wr(),
.busy(),
.addr() ,
.din(),
.dout()
);
*/
module lmx2582_spi_master (
input clk,rst,W0R1,
output reg pin_mosi,pin_sclk,pin_csn,
input pin_miso,
input wr,
output busy,
input [6:0] addr ,
input [15:0] din,
output reg [15:0] dout
);
reg [3:0] d ; always @ (posedge clk) if (rst) d<=0; else d<=d+1;
wire move = d == 0;
reg [7:0] st ;
reg [23:0] reg24 ; always@(posedge clk) if (wr&st==10) reg24 <= {W0R1,addr[6:0],din[15:0]};
reg[23:0] result24; always@(posedge clk) if (st==148 ) dout <= result24[15:0] ;
reg pin_miso_r ; always@(posedge clk) pin_miso_r<= pin_miso;
always@(posedge clk) if (st==20)pin_csn<= 1'b0 ;else if ((st==149) ||(st==0)) pin_csn<= 1'b1 ;
always@(posedge clk) if (rst) st<=0; else case(st)
0 : begin st <= 10 ; pin_mosi<=0;pin_sclk<=0;end
10 : begin pin_mosi<=0;pin_sclk<=0; if ( wr ) st<=20 ;end
20 : if ( move ) st<=21 ;
21 : if ( move ) st<=100 ;
/*
main(){
int i ,j;for(i=j=0;i<24*2;){
printf("%d: begin pin_sclk<=0; pin_mosi<= reg24[%d] ; if (move) st<=st+1 ; end \n",100+i,(23-j));++i;
printf("%d: begin pin_sclk<=1; pin_mosi<= reg24[%d] ; result24[%d] <= pin_miso_r;if (move) st<=st+1 ; end \n\n",100+i,(23-j),(23-j)); j++; ++i;
}}
*/
100: begin pin_sclk<=0; pin_mosi<= reg24[23] ; if (move) st<=st+1 ; end
101: begin pin_sclk<=1; pin_mosi<= reg24[23] ; result24[23] <= pin_miso_r;if (move) st<=st+1 ; end
102: begin pin_sclk<=0; pin_mosi<= reg24[22] ; if (move) st<=st+1 ; end
103: begin pin_sclk<=1; pin_mosi<= reg24[22] ; result24[22] <= pin_miso_r;if (move) st<=st+1 ; end
104: begin pin_sclk<=0; pin_mosi<= reg24[21] ; if (move) st<=st+1 ; end
105: begin pin_sclk<=1; pin_mosi<= reg24[21] ; result24[21] <= pin_miso_r;if (move) st<=st+1 ; end
106: begin pin_sclk<=0; pin_mosi<= reg24[20] ; if (move) st<=st+1 ; end
107: begin pin_sclk<=1; pin_mosi<= reg24[20] ; result24[20] <= pin_miso_r;if (move) st<=st+1 ; end
108: begin pin_sclk<=0; pin_mosi<= reg24[19] ; if (move) st<=st+1 ; end
109: begin pin_sclk<=1; pin_mosi<= reg24[19] ; result24[19] <= pin_miso_r;if (move) st<=st+1 ; end
110: begin pin_sclk<=0; pin_mosi<= reg24[18] ; if (move) st<=st+1 ; end
111: begin pin_sclk<=1; pin_mosi<= reg24[18] ; result24[18] <= pin_miso_r;if (move) st<=st+1 ; end
112: begin pin_sclk<=0; pin_mosi<= reg24[17] ; if (move) st<=st+1 ; end
113: begin pin_sclk<=1; pin_mosi<= reg24[17] ; result24[17] <= pin_miso_r;if (move) st<=st+1 ; end
114: begin pin_sclk<=0; pin_mosi<= reg24[16] ; if (move) st<=st+1 ; end
115: begin pin_sclk<=1; pin_mosi<= reg24[16] ; result24[16] <= pin_miso_r;if (move) st<=st+1 ; end
116: begin pin_sclk<=0; pin_mosi<= reg24[15] ; if (move) st<=st+1 ; end
117: begin pin_sclk<=1; pin_mosi<= reg24[15] ; result24[15] <= pin_miso_r;if (move) st<=st+1 ; end
118: begin pin_sclk<=0; pin_mosi<= reg24[14] ; if (move) st<=st+1 ; end
119: begin pin_sclk<=1; pin_mosi<= reg24[14] ; result24[14] <= pin_miso_r;if (move) st<=st+1 ; end
120: begin pin_sclk<=0; pin_mosi<= reg24[13] ; if (move) st<=st+1 ; end
121: begin pin_sclk<=1; pin_mosi<= reg24[13] ; result24[13] <= pin_miso_r;if (move) st<=st+1 ; end
122: begin pin_sclk<=0; pin_mosi<= reg24[12] ; if (move) st<=st+1 ; end
123: begin pin_sclk<=1; pin_mosi<= reg24[12] ; result24[12] <= pin_miso_r;if (move) st<=st+1 ; end
124: begin pin_sclk<=0; pin_mosi<= reg24[11] ; if (move) st<=st+1 ; end
125: begin pin_sclk<=1; pin_mosi<= reg24[11] ; result24[11] <= pin_miso_r;if (move) st<=st+1 ; end
126: begin pin_sclk<=0; pin_mosi<= reg24[10] ; if (move) st<=st+1 ; end
127: begin pin_sclk<=1; pin_mosi<= reg24[10] ; result24[10] <= pin_miso_r;if (move) st<=st+1 ; end
128: begin pin_sclk<=0; pin_mosi<= reg24[9] ; if (move) st<=st+1 ; end
129: begin pin_sclk<=1; pin_mosi<= reg24[9] ; result24[9] <= pin_miso_r;if (move) st<=st+1 ; end
130: begin pin_sclk<=0; pin_mosi<= reg24[8] ; if (move) st<=st+1 ; end
131: begin pin_sclk<=1; pin_mosi<= reg24[8] ; result24[8] <= pin_miso_r;if (move) st<=st+1 ; end
132: begin pin_sclk<=0; pin_mosi<= reg24[7] ; if (move) st<=st+1 ; end
133: begin pin_sclk<=1; pin_mosi<= reg24[7] ; result24[7] <= pin_miso_r;if (move) st<=st+1 ; end
134: begin pin_sclk<=0; pin_mosi<= reg24[6] ; if (move) st<=st+1 ; end
135: begin pin_sclk<=1; pin_mosi<= reg24[6] ; result24[6] <= pin_miso_r;if (move) st<=st+1 ; end
136: begin pin_sclk<=0; pin_mosi<= reg24[5] ; if (move) st<=st+1 ; end
137: begin pin_sclk<=1; pin_mosi<= reg24[5] ; result24[5] <= pin_miso_r;if (move) st<=st+1 ; end
138: begin pin_sclk<=0; pin_mosi<= reg24[4] ; if (move) st<=st+1 ; end
139: begin pin_sclk<=1; pin_mosi<= reg24[4] ; result24[4] <= pin_miso_r;if (move) st<=st+1 ; end
140: begin pin_sclk<=0; pin_mosi<= reg24[3] ; if (move) st<=st+1 ; end
141: begin pin_sclk<=1; pin_mosi<= reg24[3] ; result24[3] <= pin_miso_r;if (move) st<=st+1 ; end
142: begin pin_sclk<=0; pin_mosi<= reg24[2] ; if (move) st<=st+1 ; end
143: begin pin_sclk<=1; pin_mosi<= reg24[2] ; result24[2] <= pin_miso_r;if (move) st<=st+1 ; end
144: begin pin_sclk<=0; pin_mosi<= reg24[1] ; if (move) st<=st+1 ; end
145: begin pin_sclk<=1; pin_mosi<= reg24[1] ; result24[1] <= pin_miso_r;if (move) st<=st+1 ; end
146: begin pin_sclk<=0; pin_mosi<= reg24[0] ; if (move) st<=st+1 ; end
147: begin pin_sclk<=1; pin_mosi<= reg24[0] ; result24[0] <= pin_miso_r;if (move) st<=st+1 ; end
148: begin pin_sclk<=0; if (move) st<=st+1;end
149: begin pin_sclk<=0; if (move) st<=st+1;end
150: begin pin_sclk<=0; if (move) st<=st+1;end
151: begin if (move) st<=10; end
default st<=0;
endcase
assign busy = (wr==1) || (st!=10) ;
endmodule
都是一个套路生成的代码。
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