ARM 汇编指令条件执行详解

The condition code flags
The N, Z, C, and V (Negative, Zero, Carry and oVerflow) bits are collectively known as the condition code flags, often referred to as flags. The condition code flags in the CPSR can be tested by most instructions to determine whether the instruction is to be executed.

The condition code flags are usually modified by:
? Execution of a comparison instruction (CMN, CMP, TEQ or TST).
? Execution of some other arithmetic, logical or move instruction, where the destination register of the instruction is not R15. Most of these instructions have both a flag-preserving and a flag-setting variant, with the latter being selected by adding an S qualifier to the instruction mnemonic. Some of these instructions only have a flag-preserving version. This is noted in the individual instruction descriptions.
In either case, the new condition code flags (after the instruction has been executed) usually mean:

N Is set to bit 31 of the result of the instruction. If this result is regarded as a two's complement signed integer, then N = 1 if the result is negative and N = 0 if it is positive or zero.

Z Is set to 1 if the result of the instruction is zero (this often indicates an equal result from a comparison), and to 0 otherwise.

C Is set in one of four ways:
? For an addition, including the comparison instruction CMN, C is set to 1 if the addition
produced a carry (that is, an unsigned overflow), and to 0 otherwise.
? For a subtraction, including the comparison instruction CMP, C is set to 0 if the
subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise.
? For non-addition/subtractions that incorporate a shift operation, C is set to the last bit
shifted out of the value by the shifter.
? For other non-addition/subtractions, C is normally left unchanged (but see the
individual instruction descriptions for any special cases).

V Is set in one of two ways:
? For an addition or subtraction, V is set to 1 if signed overflow occurred, regarding the
operands and result as two's complement signed integers.
? For non-addition/subtractions, V is normally left unchanged (but see the individual
instruction descriptions for any special cases).
The flags can be modified in these additional ways:
? Execution of an MSR instruction, as part of its function of writing a new value to the CPSR or SPSR.
? Execution of MRC instructions with destination register R15. The purpose of such instructions is to
transfer coprocessor-generated condition code flag values to the ARM processor.
? Execution of some variants of the LDM instruction. These variants copy the SPSR to the CPSR, and
their main intended use is for returning from exceptions.
? Execution of an RFE instruction in a privileged mode that loads a new value into the CPSR from
memory.
? Execution of flag-setting variants of arithmetic and logical instructions whose destination register is R15. These also copy the SPSR to the CPSR, and are intended for returning from exceptions.