while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET){}卡死
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) != SET){}卡死
//
RCC_PLLCmd(ENABLE);
RCC_PLLConfig(RCC_PLLSource_PREDIV1,RCC_CFGR_PLLMULL6);
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET){}
如上,问题出在哪里呢?
问题出在PLL使能先后问题。
注意,PLL参数配置时,只能是disable状态,否则无效。所以,应该先配置,再使能,代码如下
RCC_PLLConfig(RCC_PLLSource_PREDIV1,RCC_CFGR_PLLMULL6);
RCC_PLLCmd(ENABLE);
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET){}
下面是标准库的源代码,请看第二行的注释:This function must be used only when the PLL is disabled.
/**
* @brief Configures the PLL clock source and multiplication factor.
* @note This function must be used only when the PLL is disabled.
*
* @param RCC_PLLSource: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
* @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
* @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
* PLL source).
*
* @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
* This parameter can be RCC_PLLMul_x where x:[2,16]
*
* @retval None
*/
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
{
/* Check the parameters */
assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
/* Clear PLL Source [16] and Multiplier [21:18] bits */
RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
/* Set the PLL Source and Multiplier */
RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
}
/**
* @brief Enables or disables the PLL.
* @note After enabling the PLL, the application software should wait on
* PLLRDY flag to be set indicating that PLL clock is stable and can
* be used as system clock source.
* @note The PLL can not be disabled if it is used as system clock source
* @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
* @param NewState: new state of the PLL.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void RCC_PLLCmd(FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
RCC->CR |= RCC_CR_PLLON;
}
else
{
RCC->CR &= ~RCC_CR_PLLON;
}
}