SystemVerilog Assertion guide

1. An assertion is a statement of fact--声明某种属性为真

 

2. Assertion coverage 报告 never triggered, vacuous success（前提从来没满足过）, not tested branch（某个条件分支没有有效过）.

 

3. Design Engineer用 assert来检查

     1）模块输入有没有X，Z态

     2）发现design不支持的用法，报警

     3）设计时的假设，包括接口的时序

     4） buffer/FIFO 的overflow

     5） 一些不能出现的情况，譬如read和write同时有效

     6） 握手总是能够完成 （ack总是跟在req之后）

     7） case语句不会进入未曾预料的区域

     8） not duplicate RTL.   (monitor output changes, and verifiy the input value will cause that changes)

 

4. verification Engineer 用 assert 来

     1） 进行functional coverage检测

     2） 衡量仲裁的公平性。。。

 

5. 两种类型的assertion

     1） immediate   

            [ name : ] assert ( expression ) [ pass_statement ] [ else fail_statement ]

            一般只是dynamic cast和randomize时使用，只在当前时刻做一次check

 

     2） concurrent

            [ name : ] assert property ( property_specification ) pass_statement [ else fail_statement ]

 

            property p1; @sample_signal disable iff ( expression ) // optional disable condition property_expression_or_sequence endproperty assert property ( p1 ) optional_action_block ;

            是一种持续属性，在整个simulation阶段都做check。如果没有指定事件，那么就是在每个point都check。一般独立于initial和always快之外，但是放在initial 块中就只检测一次（第一次运行时刻），如果放在always块中每次事件发生时检测。

 

6. 四种assertion严重度

    1） $fatal [ ( finish_number, “message”, message_arguments ) ];

    2） $error [ ( “message”, message_arguments ) ] ;

    3） $warning [ ( “message”, message_arguments ) ] ;

    4） $info [ ( “message”, message_arguments ) ] ;

 

7. assertion的分类

    1） Invariant assertions

    2） Sequential assertions

    3） Eventuality assertions

 

8. The Assertions Test Plan should be developed before any design code is written!

 

RAM assertions

Functionality to Verify	Assertion Type	Assigned To
!rdN and !wrN are mutually exclusive	invariant	design team
address never has any X or Z bits when reading from or writing to the RAM	invariant	design team
data never has any X or Z bits when reading from or writing to the RAM	sequential	design team

 

9. Simulators might report an assertion that never completed as a failure or as an uncompleted assertion

 

 

10. declarative and procedural concurrent assertion

      1) declarative:   runs thoughout the simulation and fires every clock cycles

      2) procedural:    runs when calls with parallel thread

 

11. 条件 sequence 用implication operators

       1） |->   overlapping

       2） |=>  non-overlapping  （助记： 等号意味着等一个cycle）

 

12. seqence value change

       1)  $rose(expression)    

       2)  $fall(expression)

       3)  $stable(expression)

 

13.  consecutive sequence & non-consecutive sequence

       non-consecutive（goto repetition）:                        a ##1 b[->1:3] ##1 c  // E.g. a !b b b !b !b b c

       non-consecutive（non-consecutive repetition）：    a ##1 b [=1:3] ##1 c // E.g. a !b b b !b !b b !b !b c

 

14. Testing for a Cause

       SVA provides three ways to look back into the past