VCS has a built-in sparse memory model that is ideal for what Luke is proposing. VCS will only allocate memory for the entries that are used during simulation. The performance is slightly slower than a standard Verilog memory, but with vastly larger memory ranges. The sparse memory model is native to VCS, and does not require any PLI application. Just declare your memory as:
reg /* sparse */ [31:0] memory [0:3_000_000_000];