assertions 使用问答

1.  如何防止在simulation结束仍然还未结束的assertion打印出消息？

VCS supports disabling the SVA unfinished message reporting  at the end of simulation, please do as follows:

1)      Add VCS compile option  “vcs  -assert enable_diag”, which means, enable runtime SVA options

2)      Add VCS runtime option “simv -assert nopostproc” , which means, disable VCS from reporting messages about unfinished assertions at the end of simulation.

 

Then the unfinished message will not be printed on the screen.

2. 如何对assertion进行分类？

DVE supports assertion category, you can use this feature as following:

 

Define assertions with category attribute, for example:

    property hsync;

     @(posedge dClk) (dReset_n) throughout

     $rose(dHsync)|-> ##HPULSE $fell(dHsync);

    endproperty

 

   (* category=1 *) HsyncWidth: assert property ( hsync);

 

    property vsync;

     @(posedge dClk) (dReset_n) throughout

     $rose(dVsync)|-> ##VPULSE $fell(dVsync);

    endproperty

 

     (* category=2 *)  VsyncWidth: assert property ( vsync);

3. cover group 在类中可以有多个instance吗？ cover group 可以带参数吗？

VCS supports coverage groups with arguments, for example:

 

class Scoreboard extends vmm_xactor;

 

covergroup sb_arg_cov (int low, int high);

   covp_blue:coverpoint obj.blu {

     bins covb_blue0 ={[low:high]};

     bins covb_blue1 ={[low+100:high+100]};

 

  }

endgroup:sb_arg_cov

 

 

  function new(string instance = "class",

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