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RSS订阅原创 clock divider RTL 如何描述？
//function: randome divider clk_out= clk/k1//note// k1: must bigger than 1 (>=2)// div_change_en: enable signal for change the k1module clock_div( //input clk, //input clk rs
2011-06-14 18:14:00
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原创 vcs option +udpsched in gate level simulation without delay
When the udpsched switch is used, VCS treats the event to update the output of a sequential udp as if it was using a non-blocking assignment. This matches the scheduling of non-blocking assignments wi
2011-06-10 18:03:00
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