hdlbits
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night_Ray
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HDLBits刷题Day01
0~10Zero要求输出0;考察了Quartus中,不给变量赋值默认值为0;模块声明语句中不需要加分号;//赋0module top_module( output zero); assign zero=0; //或者assign zero=1'b0;endmoduleList item原创 2021-01-07 13:51:54 · 175 阅读 · 0 评论 -
HDLBits刷题Day02
10~10. Vector011.Vector1--Vector in more detail12.Vector--Vector PartSelect13.Vectorgates--Bitwise operators14.Four-input gates15.Vector3--16.Vector--reverse10. Vector0数组类似C语言type [upper:lower] vector_namewire [99:0] my_vector; // Declare a 100-el原创 2021-01-08 15:09:13 · 182 阅读 · 0 评论 -
HDLBits刷题Day03
20~20.Module pos21.Module name22.Three--Module23.Module and vector24.Adder125.Adder220.Module posmodule top_module ( input a, input b, input c, input d, output out1, output out2 ); mod_a inst1 (out1,out2,a,b,c,d); //和19题不原创 2021-01-08 21:25:33 · 166 阅读 · 0 评论 -
HDLBits刷题Day04
28~36 Always块,if else,case,casez选择语句28.Always blocks29.Always blocks230.Always_if31.Always if2--latch(锁存器)32 Always case33.Always case-priority encoder(优先编码器)34.priority encoder--caseZ35.Always nolatches强烈建议大家去看看HDLBits 中文导学,原文在知乎链接: link.28.Always bloc原创 2021-01-09 17:11:01 · 171 阅读 · 0 评论 -
HDLBits刷题Day05
3636.Conditional ternary operator37 Reduction operator--按位(归约)运算符36.Conditional ternary operator其实也就是c语言中条件运算符module top_module ( input [7:0] a, b, c, d, output [7:0] min);// wire [7:0] result1,result2; assign result1 = (a<b)? a:b;原创 2021-01-12 13:06:26 · 167 阅读 · 0 评论 -
HDLBits刷题Day06
43~ 组合逻辑基本门电路43.Wire44.GND45.强烈建议大家去看看HDLBits 中文导学,原文在知乎链接: link.43.Wiremodule top_module ( input in, output out); assign out=in;endmodule44.GNDmodule top_module ( output out);assign out=1'b0;endmodule45....原创 2021-01-13 14:03:58 · 132 阅读 · 0 评论 -
HDLBits刷题Day07
60~71 多路选择器/加法器60.Mux2to161.2-to-1 bus multiplexer (Mux2to1v)62.9-to-1 multiplexer (Mux9to1v)63.256-to-1 multiplexer (Mux256to1)64.256-to-1 4-bit multiplexer (Mux256to1v)65.Half adder(半加器)66.Full adder(全加器)67.3-bit binary adder68.Adder-4-bit 全加器69.Signed a原创 2021-01-14 17:28:04 · 249 阅读 · 0 评论 -
HDLBits刷题Day08
72~卡诺图72.3-variable Karnaugh map强烈建议大家去看看HDLBits 中文导学,原文在知乎链接: link.72.3-variable Karnaugh mapmodule top_module( input a, input b, input c, output out ); assign out=b|(!b&c)|(a&!b);endmodule我的一开始化简出来,并不是最简的,module top原创 2021-01-15 15:27:30 · 216 阅读 · 0 评论 -
HDLBits刷题Day09
80~触发器和锁存器80.D flip-flop (Dff)81.D flip-flops82.DFF with reset (Dff8r)83.DFF with reset value84.DFF with asynchronous reset85.DFF with byte enable86.D latch(D锁存器)87.DFF(异步)88.DFF(同步)89.DFF+gate90.Mux and DFF91.Mux and DFF92.DFFS and gates93.Create circuit原创 2021-01-18 14:42:43 · 281 阅读 · 0 评论 -
HDLBits刷题Day10
98~104 计数器 98.Four-bit binary counter99.Decade counter99.Decade counter again100.Slow decade counter101.Counter 1-12(没太看懂)102.Counter 1000103.4-digit decimal counter104.12-hour clock强烈建议大家去看看HDLBits 中文导学,原文在知乎链接: link.98.Four-bit binary counteralways@(原创 2021-01-21 16:06:05 · 206 阅读 · 0 评论 -
HDLBits刷题Day11
106 移位寄存器106.4-bit shift register强烈建议大家去看看HDLBits 中文导学,原文在知乎链接: link.106.4-bit shift register原创 2021-03-12 14:52:59 · 277 阅读 · 0 评论 -
HDLBits刷题Day12
时序逻辑生成输出115.Rule90116.Rule110强烈建议大家去看看HDLBits 中文导学,原文在知乎链接: link.115.Rule90module top_module( input clk, input load, input [511:0] data, output [511:0] q ); int i; always@(posedge clk) if(load) q<=data;原创 2021-03-16 16:32:30 · 153 阅读 · 0 评论 -
HDLBits刷题Day13
大Boss—Finite State Machines有穷状态机118. Simple FSM 1 (asynchronous reset)119.Simple FSM 1 (synchronous reset)120.Simple FSM 2 (asynchronous reset)121.Simple FSM 2 (synchronous reset)122.Simple state transitions 3123.Simple one-hot state transitions 3124.Simpl原创 2022-05-17 13:33:14 · 119 阅读 · 0 评论