`timescale 1 ns / 1 ns
module monitor_cnt (
//cbus
input clk_cbus,
input rst_cbus,
input ilbus_req,
input ilbus_rw,
input [15:0] ilbus_addr,
input [31:0] ilbus_wdata,
output olbus_ack,
output [31:0] olbus_rdata,
//ext
input ilbus_req_ext,
output olbus_ack_ext,
output [31:0] olbus_rdata_ext,
//debug
output [11:0] table3_cnt_inused,
output [11:0] table3_cnt_pushout,
output [11:0] table5_cnt_inused,
output [11:0] table5_cnt_pushout,
//user
input sys_clk,
input sys_rst,
input [8:0] up_din,
input up_din_err,
input up_din_wen,
input [8:0] dn_din,
input dn_din_err,
input dn_din_wen
);
//====================================
// define
//====================================
wire up_broadcast_flag;
wire up_ip0800_flag;
wire [10:0] up_byte_cnt;
wire [47:0] up_src_mac;
wire up_pkt_wen;
wire [15:0] up_iphd_len;
wire [07:0] up_protocol;
wire [31:0] up_src_ip;
wire [31:0] up_dst_ip;
wire [15:0] up_src_port;
wire [15:0] up_dst_port;
wire up_ip_noseg;
wire up_hashid_p3;
wire [4:0] up_hashid_p5;
wire up_info_wen;
wire dn_broadcast_flag;
wire dn_ip0800_flag;
wire [10:0] dn_byte_cnt;
wire [47:0] dn_src_mac;
wire dn_pkt_wen;
wire [15:0] dn_iphd_len;
wire [07:0] dn_protocol;
wire [31:0] dn_src_ip;
wire [31:0] dn_dst_ip;
wire [15:0] dn_src_port;
wire [15:0] dn_dst_port;
wire dn_ip_noseg;
wire dn_hashid_p3;
wire [4:0] dn_hashid_p5;
wire dn_info_wen;
// 1min timer
wire min_pls;
reg min_pls_reg;
wire tensec_pls;
reg tensec_pls_reg;
// total cnt
reg up_pkt_wen_d1;
reg up_pkt_wen_d2;
reg up_pkt_wen_d3;
reg up_pkt_wen_d4;
reg up_pkt_wen_d5;
reg dn_pkt_wen_d1;
reg mac1_match_part1;
reg mac1_match_part2;
reg mac1_match_part3;
reg mac2_match_part1;
reg mac2_match_part2;
reg mac2_match_part3;
reg mac1_match;
reg mac2_match;
reg mac1_dsp_ena;
reg mac1_dsp_clr;
reg mac2_dsp_ena;
reg mac2_dsp_clr;
reg mac1_valid;
reg [47:0] mac1_mac;
reg [3:0] mac1_toutcnt;
reg mac2_valid;
reg [47:0] mac2_mac;
reg [3:0] mac2_toutcnt;
reg mac1_dsp_clr_pls;
reg mac1_dsp_ena_pls;
reg mac2_dsp_clr_pls;
reg mac2_dsp_ena_pls;
wire [47:0] up_pktcnt_mac1;
wire [47:0] up_pktcnt_mac2;
wire [47:0] up_bytecnt_mac1;
wire [47:0] up_bytecnt_mac2;
wire [47:0] dn_pktcnt;
wire [47:0] dn_bytecnt;
// cnt per 1min
wire [47:0] up_pktcnt_min;
wire [47:0] up_bytecnt_min;
wire [47:0] dn_pktcnt_min;
wire [47:0] dn_bytecnt_min;
reg [47:0] up_pktcnt_min_reg;
reg [47:0] up_bytecnt_min_reg;
reg [47:0] dn_pktcnt_min_reg;
reg [47:0] dn_bytecnt_min_reg;
// cnt not ip0800
wire [47:0] up_pktcnt_not0800;
wire [47:0] up_bytecnt_not0800;
wire [47:0] dn_pktcnt_not0800;
wire [47:0] dn_bytecnt_not0800;
// three tuple,128*chan
reg cnt01_flag;
reg up_src_ip_is00;
reg up_src_ip_isFF;
reg up_dst_ip_is00;
reg up_dst_ip_isFF;
reg up_protocol_istcpudp;
reg up_ip_match_p3;
reg up_ip_match_p5;
reg dn_src_ip_is00;
reg dn_src_ip_isFF;
reg dn_dst_ip_is00;
reg dn_dst_ip_isFF;
reg dn_protocol_istcpudp;
reg dn_ip_match_p3;
reg dn_ip_match_p5;
reg up_info_wen_d1;
reg dn_info_wen_d1;
reg [143:0] fifo_din;
reg fifo_wen_p3;
reg fifo_wen_p5;
wire [71:0] u1_doutb;
wire [71:0] u2_doutb;
wire [71:0] u3_doutb;
// local bus
reg [15:0] lbus_rdaddr;
reg lbus_req_d1;
reg lbus_req_d2;
reg lbus_req_d3;
reg lbus_req_d4;
reg lbus_req_d5;
reg lbus_req_d6;
reg lbus_ack;
reg [31:0] lbus_rdata;
//load readdata
reg lbus_ack_pre1_chan;
reg lbus_ack_pre1_reg;
reg lbus_ack_pre2_dsp;
reg lbus_ack_pre1_upmac1;
reg lbus_ack_pre1_upmac2;
reg [71:0] lbus1_doutb_L72;
reg [71:0] lbus2_doutb_L72;
reg [71:0] lbus3_doutb_L72;
reg [15:0] up_bytecnt_min_reg_H16;
reg [15:0] up_pktcnt_min_reg_H16;
reg [15:0] dn_bytecnt_min_reg_H16;
reg [15:0] dn_pktcnt_min_reg_H16;
reg [47:0] up_bytecnt_not0800_L48;
reg [47:0] up_pktcnt_not0800_L48;
reg [47:0] dn_bytecnt_not0800_L48;
reg [47:0] dn_pktcnt_not0800_L48;
reg [31:0] mac1_mac_L32;
reg [47:0] up_bytecnt_mac1_L48;
reg [47:0] up_pktcnt_mac1_L48;
reg [31:0] mac2_mac_L32;
reg [47:0] up_bytecnt_mac2_L48;
reg [47:0] up_pktcnt_mac2_L48;
reg [47:0] dn_bytecnt_L48;
reg [47:0] dn_pktcnt_L48;
//====================================
// process
//====================================
monitor_cnt_chan monitor_cnt_chan_up (
//system
/*input */ .sys_clk (sys_clk ),
/*input */ .sys_rst (sys_rst ),
/*input [8:0] */ .din (up_din ),
/*input */ .din_err (up_din_err ),
/*input */ .din_wen (up_din_wen ),
/* */
/*output reg */ .broadcast_flag (up_broadcast_flag ),
/*output reg */ .ip0800_flag (up_ip0800_flag ),
/*output reg [10:0] */ .byte_cnt (up_byte_cnt ),
/*output reg [47:0] */ .src_mac (up_src_mac ),
/*output reg */ .pkt_wen (up_pkt_wen ),
/* */
/*output reg [15:0] */ .iphd_len (up_iphd_len ),
/*output reg [07:0] */ .protocol (up_protocol ),
/*output reg [31:0] */ .src_ip (up_src_ip ),
/*output reg [31:0] */ .dst_ip (up_dst_ip ),
/*output reg [15:0] */ .src_port (up_src_port ),
/*output reg [15:0] */ .dst_port (up_dst_port ),
/*output reg */ .ip_noseg (up_ip_noseg ),
/*output reg */ .hashid_p3 (up_hashid_p3 ),
/*output reg [4:0] */ .hashid_p5 (up_hashid_p5 ),
/*output reg */ .info_wen (up_info_wen )
);
monitor_cnt_chan monitor_cnt_chan_dn (
//system
/*input */ .sys_clk (sys_clk ),
/*input */ .sys_rst (sys_rst ),
/*input [8:0] */ .din (dn_din ),
/*input */ .din_err (dn_din_err ),
/*input */ .din_wen (dn_din_wen ),
/* */
/*output reg */ .broadcast_flag (dn_broadcast_flag ),
/*output reg */ .ip0800_flag (dn_ip0800_flag ),
/*output reg [10:0] */ .byte_cnt (dn_byte_cnt ),
/*output reg [47:0] */ .src_mac (dn_src_mac ),
/*output reg */ .pkt_wen (dn_pkt_wen ),
/* */
/*output reg [15:0] */ .iphd_len (dn_iphd_len ),
/*output reg [07:0] */ .protocol (dn_protocol ),
/*output reg [31:0] */ .src_ip (dn_src_ip ),
/*output reg [31:0] */ .dst_ip (dn_dst_ip ),
/*output reg [15:0] */ .src_port (dn_src_port ),
/*output reg [15:0] */ .dst_port (dn_dst_port ),
/*output reg */ .ip_noseg (dn_ip_noseg ),
/*output reg */ .hashid_p3 (dn_hashid_p3 ),
/*output reg [4:0] */ .hashid_p5 (dn_hashid_p5 ),
/*output reg */ .info_wen (dn_info_wen )
);
//====================================
// 1min timer
//====================================
// 1min = 60*1000*1000*1000 = 12*1000*1000*1000clks=48'h2CB417800
COUNTER_TC_MACRO #(
.COUNT_BY(48'h000000000001), // Count by value
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.DIRECTION("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC("TRUE"), // Reset counter upon terminal count, "TRUE" or "FALSE"
`ifdef SIM_ON
.TC_VALUE(48'h000000002EE0), // Terminal count value
`else
.TC_VALUE(48'h0002CB417800), // Terminal count value
`endif
.WIDTH_DATA(48) // Counter output bus width, 1-48
) COUNTER_TC_MACRO_inst (
.Q(), // Counter output bus, width determined by WIDTH_DATA parameter
.TC(min_pls), // 1-bit terminal count output, high = terminal count is reached
.CLK(sys_clk), // 1-bit positive edge clock input
.CE(1'b1), // 1-bit active high clock enable input
.RST(sys_rst) // 1-bit active high synchronous reset
);
always @ (posedge sys_clk)begin
min_pls_reg <= min_pls;
end
//====================================
// 10sec timer
//====================================
// 1min = 60*1000*1000*1000 = 12*1000*1000*1000clks=48'h2CB417800
// 10sec = 10*1000*1000*1000 = 2*1000*1000*1000clks=48'h077359400
COUNTER_TC_MACRO #(
.COUNT_BY(48'h000000000001), // Count by value
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.DIRECTION("UP"), // Counter direction, "UP" or "DOWN"
.RESET_UPON_TC("TRUE"), // Reset counter upon terminal count, "TRUE" or "FALSE"
`ifdef SIM_ON
//.TC_VALUE(48'h000000002EE0), // Terminal count value
.TC_VALUE(48'h0000000007D0), // Terminal count value
`else
//.TC_VALUE(48'h0002CB417800), // Terminal count value
.TC_VALUE(48'h000077359400), // Terminal count value
`endif
.WIDTH_DATA(48) // Counter output bus width, 1-48
) COUNTER_TC_MACRO_10sec (
.Q(), // Counter output bus, width determined by WIDTH_DATA parameter
.TC(tensec_pls), // 1-bit terminal count output, high = terminal count is reached
.CLK(sys_clk), // 1-bit positive edge clock input
.CE(1'b1), // 1-bit active high clock enable input
.RST(sys_rst) // 1-bit active high synchronous reset
);
always @ (posedge sys_clk)begin
tensec_pls_reg <= tensec_pls;
end
//====================================
// total cnt
//====================================
always @ (posedge sys_clk)begin
up_pkt_wen_d1 <= up_pkt_wen;
up_pkt_wen_d2 <= up_pkt_wen_d1;
up_pkt_wen_d3 <= up_pkt_wen_d2;
up_pkt_wen_d4 <= up_pkt_wen_d3;
up_pkt_wen_d5 <= up_pkt_wen_d4;
dn_pkt_wen_d1 <= dn_pkt_wen;
end
always @ (posedge sys_clk)begin
if(up_pkt_wen)begin
mac1_match_part1 <= (up_src_mac[15:00]==mac1_mac[15:00]);
mac1_match_part2 <= (up_src_mac[31:16]==mac1_mac[31:16]);
mac1_match_part3 <= (up_src_mac[47:32]==mac1_mac[47:32]);
mac2_match_part1 <= (up_src_mac[15:00]==mac2_mac[15:00]);
mac2_match_part2 <= (up_src_mac[31:16]==mac2_mac[31:16]);
mac2_match_part3 <= (up_src_mac[47:32]==mac2_mac[47:32]);
end
if(up_pkt_wen_d1)begin
mac1_match <= mac1_match_part1 & mac1_match_part2 & mac1_match_part3 & mac1_valid;
mac2_match <= mac2_match_part1 & mac2_match_part2 & mac2_match_part3 & mac2_valid;
end
if(sys_rst | up_pkt_wen_d5)begin
{mac1_dsp_ena,mac1_dsp_clr} <= {1'b0,1'b0};
{mac2_dsp_ena,mac2_dsp_clr} <= {1'b0,1'b0};
end else if(up_pkt_wen_d2 & mac1_match)begin
{mac1_dsp_ena,mac1_dsp_clr} <= {1'b1,1'b0};
{mac2_dsp_ena,mac2_dsp_clr} <= {1'b0,1'b0};
end else if(up_pkt_wen_d2 & mac2_match)begin
{mac1_dsp_ena,mac1_dsp_clr} <= {1'b0,1'b0};
{mac2_dsp_ena,mac2_dsp_clr} <= {1'b1,1'b0};
end else if(up_pkt_wen_d2==1'b1 && (mac1_valid&mac2_valid)==1'b1)begin //2'b11
if(mac1_toutcnt>=mac2_toutcnt)begin
{mac1_dsp_ena,mac1_dsp_clr} <= {1'b1,1'b1};
{mac2_dsp_ena,mac2_dsp_clr} <= {1'b0,1'b0};
end else begin
{mac1_dsp_ena,mac1_dsp_clr} <= {1'b0,1'b0};
{mac2_dsp_ena,mac2_dsp_clr} <= {1'b1,1'b1};
end
end else if(up_pkt_wen_d2==1'b1 && (mac1_valid|mac2_valid)==1'b1)begin //2'b01 or 2'b10
if(mac2_valid)begin
{mac1_dsp_ena,mac1_dsp_clr} <= {1'b1,1'b1};
{mac2_dsp_ena,mac2_dsp_clr} <= {1'b0,1'b0};
end else begin
{mac1_dsp_ena,mac1_dsp_clr} <= {1'b0,1'b0};
{mac2_dsp_ena,mac2_dsp_clr} <= {1'b1,1'b1};
end
end else if(up_pkt_wen_d2==1'b1 && (mac1_valid|mac2_valid)==1'b0)begin //2'b00
{mac1_dsp_ena,mac1_dsp_clr} <= {1'b1,1'b1};
{mac2_dsp_ena,mac2_dsp_clr} <= {1'b0,1'b0};
end
end
//mac1
always @ (posedge sys_clk)begin
if(sys_rst)begin
mac1_valid <= 1'b0;
end else if(mac1_dsp_clr_pls)begin
mac1_valid <= 1'b0;
end else if(mac1_dsp_ena_pls & (~mac1_dsp_ena))begin
mac1_valid <= 1'b1;
end else if(min_pls_reg==1'b1 && mac1_toutcnt>=4'hA)begin
mac1_valid <= 1'b0;
end
if(mac1_dsp_ena_pls & (~mac1_dsp_ena))begin
mac1_mac <= up_src_mac;
end
end
always @ (posedge sys_clk)begin
if(sys_rst)begin
mac1_toutcnt <= 4'b0;
end else if((mac1_dsp_ena & up_pkt_wen_d5) || (mac1_valid==1'b0))begin
mac1_toutcnt <= 4'b0;
end else if(min_pls_reg)begin
mac1_toutcnt <= mac1_toutcnt + 1'b1;
end
end
//mac2
always @ (posedge sys_clk)begin
if(sys_rst)begin
mac2_valid <= 1'b0;
end else if(mac2_dsp_clr_pls)begin
mac2_valid <= 1'b0;
end else if(mac2_dsp_ena_pls & (~mac2_dsp_ena))begin
mac2_valid <= 1'b1;
end else if(min_pls_reg==1'b1 && mac2_toutcnt>=4'hA)begin
mac2_valid <= 1'b0;
end
if(mac2_dsp_ena_pls & (~mac2_dsp_ena))begin
mac2_mac <= up_src_mac;
end
end
always @ (posedge sys_clk)begin
if(sys_rst)begin
mac2_toutcnt <= 4'b0;
end else if((mac2_dsp_ena & up_pkt_wen_d5) || (mac2_valid==1'b0))begin
mac2_toutcnt <= 4'b0;
end else if(min_pls_reg)begin
mac2_toutcnt <= mac2_toutcnt + 1'b1;
end
end
always @ (posedge sys_clk)begin
mac1_dsp_clr_pls <= mac1_dsp_clr & up_pkt_wen_d3;
mac1_dsp_ena_pls <= mac1_dsp_ena & (up_pkt_wen_d4|up_pkt_wen_d5);
mac2_dsp_clr_pls <= mac2_dsp_clr & up_pkt_wen_d3;
mac2_dsp_ena_pls <= mac2_dsp_ena & (up_pkt_wen_d4|up_pkt_wen_d5);
end
//up cnt : mac1/mac2
ADDSUB_MACRO #(
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.LATENCY(2), // Desired clock cycle latency, 0-2
.WIDTH(48) // Input / output bus width, 1-48
) u_up_pktcnt_mac1 (
.CARRYOUT(), // 1-bit carry-out output signal endmodule
.RESULT(up_pktcnt_mac1), // Add/sub result output, width defined by WIDTH parameter
.A(up_pktcnt_mac1), // Input A bus, width defined by WIDTH parameter
.ADD_SUB(1'b1), // 1-bit add/sub input, high selects add, low selects subtract
.B(48'h1), // Input B bus, width defined by WIDTH parameter
.CARRYIN(1'b0), // 1-bit carry-in input
.CE(mac1_dsp_ena_pls), // 1-bit clock enable input
.CLK(sys_clk), // 1-bit clock input
.RST(mac1_dsp_clr_pls) // 1-bit active high synchronous reset
);
ADDSUB_MACRO #(
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.LATENCY(2), // Desired clock cycle latency, 0-2
.WIDTH(48) // Input / output bus width, 1-48
) u_up_pktcnt_mac2 (
.CARRYOUT(), // 1-bit carry-out output signal endmodule
.RESULT(up_pktcnt_mac2), // Add/sub result output, width defined by WIDTH parameter
.A(up_pktcnt_mac2), // Input A bus, width defined by WIDTH parameter
.ADD_SUB(1'b1), // 1-bit add/sub input, high selects add, low selects subtract
.B(48'h1), // Input B bus, width defined by WIDTH parameter
.CARRYIN(1'b0), // 1-bit carry-in input
.CE(mac2_dsp_ena_pls), // 1-bit clock enable input
.CLK(sys_clk), // 1-bit clock input
.RST(mac2_dsp_clr_pls) // 1-bit active high synchronous reset
);
ADDSUB_MACRO #(
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.LATENCY(2), // Desired clock cycle latency, 0-2
.WIDTH(48) // Input / output bus width, 1-48
) u_up_bytecnt_mac1 (
.CARRYOUT(), // 1-bit carry-out output signal endmodule
.RESULT(up_bytecnt_mac1), // Add/sub result output, width defined by WIDTH parameter
.A(up_bytecnt_mac1), // Input A bus, width defined by WIDTH parameter
.ADD_SUB(1'b1), // 1-bit add/sub input, high selects add, low selects subtract
.B({37'h0,up_byte_cnt}), // Input B bus, width defined by WIDTH parameter
.CARRYIN(1'b0), // 1-bit carry-in input
.CE(mac1_dsp_ena_pls), // 1-bit clock enable input
.CLK(sys_clk), // 1-bit clock input
.RST(mac1_dsp_clr_pls) // 1-bit active high synchronous reset
);
ADDSUB_MACRO #(
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.LATENCY(2), // Desired clock cycle latency, 0-2
.WIDTH(48) // Input / output bus width, 1-48
) u_up_bytecnt_mac2 (
.CARRYOUT(), // 1-bit carry-out output signal endmodule
.RESULT(up_bytecnt_mac2), // Add/sub result output, width defined by WIDTH parameter
.A(up_bytecnt_mac2), // Input A bus, width defined by WIDTH parameter
.ADD_SUB(1'b1), // 1-bit add/sub input, high selects add, low selects subtract
.B({37'h0,up_byte_cnt}), // Input B bus, width defined by WIDTH parameter
.CARRYIN(1'b0), // 1-bit carry-in input
.CE(mac2_dsp_ena_pls), // 1-bit clock enable input
.CLK(sys_clk), // 1-bit clock input
.RST(mac2_dsp_clr_pls) // 1-bit active high synchronous reset
);
//dn cnt
ADDSUB_MACRO #(
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.LATENCY(2), // Desired clock cycle latency, 0-2
.WIDTH(48) // Input / output bus width, 1-48
) u_dn_pktcnt (
.CARRYOUT(), // 1-bit carry-out output signal endmodule
.RESULT(dn_pktcnt), // Add/sub result output, width defined by WIDTH parameter
.A(dn_pktcnt), // Input A bus, width defined by WIDTH parameter
.ADD_SUB(1'b1), // 1-bit add/sub