arm CP15 c1 Control Register

The Control Register provides control and configuration of:

• memory alignment, endianness, protection, and fault behavior

• MMU and cache enables

• interrupts

• the location for exception vectors

• program flow prediction.

The Control Register is:

• in CP15 c1

• a 32 bit register,

• accessible in privileged modes only.

You can use the Control Register to enable and disable system configuration options. You can access the Control Register by reading or writing CP15 c1 with the CRm and Opcode_2 fields set to 0:

MRC p15,0,<Rd>,c1,c0,0; Read Control Register configuration data

MCR p15,0,<Rd>,c1,c0,0; Write Control Register configuration data

It is recommended that you access this register using a read-modify-write sequence.

All defined control bits are set to zero on Reset except:

• The V bit. At reset, this bit is set to 0 if the VINITHI signal is LOW, or 1 if the VINITHI signal is HIGH.

• The U and EE bits in the CP15 Control Register and the E Bit in the CPSR/SPSR. The reset values of these bits depend on the system configuration pins, CFGEND. Table 3.18 shows these reset values.

  Table 3.18. CFGEND, EE, U, and E bit values

  CFGEND [1:0]	CP15 Control Register		CPSR/SPSR
  	EE bit	U bit	E bit
  00	0	0	0
  01 Reserved	-	-	-
  10	0	1	0
  11	1	1	1

  
  

Table 3.19 shows endianness and alignment control options.

Table 3.19. Endianness and alignment control options

U	A	E	Instruction endianness	Data endianness	Unaligned behavior	Description
0	0	0	LE	LE	Rotated LDR	Legacy LE
0	0	1	-	-	-	Reserved
0	1	0	LE	LE	Data Abort	Modulo 8 LDRD/STRD doubleword alignment checking
0	1	1	LE	BE-8	Data Abort	Modulo 8 LDRD/STRD doubleword alignment checking
1	0	0	LE	LE	Unaligned	Unaligned access permitted
1	0	1	LE	BE-8	Unaligned	Unaligned access permitted
1	1	0	LE	LE	Data Abort	Modulo 4 alignment checking
1	1	1	LE	BE-8	Data Abort	Modulo 4 alignment checking

Figure 3.18 shows the format of the Control Register.

Figure 3.18. Control Register format

Table 3.20 shows the bit assignment of the Control Register.

Table 3.20. Control Register bit functions

Bits	Field	Function
[31:30]	-	Reserved. SBZ/RAZ.
[29]	Force AP	This bit controls the Force AP functionality in the MMU that generates Access Bit faults, see Access permissionsAccess permissions: 0 = Force AP disabled, reset value 1 = Force AP enabled.
[28]	TEX Remap	This bit controls the TEX remap functionality in the MMU, see Memory region attributes: 0 = TEX remap disabled. Normal ARMv6 behavior, reset value. 1 = TEX remap enabled. TEX[2:1] become page table bits for OS.
[27]	NMFI	NMFI bit: 0 = normal FIQ behavior 1 = FIQs behave as NMFIs.
[26]	-	Reserved. SBZ/RAZ.
[25]	EE	This bit determines the setting of the CPSR E bit on taking an exception: 0 = CPSR E bit is set to 0 on taking an exception 1 = CPSR E bit is set to 1 on taking an exception.
[24]	-	Reserved. SBZ/RAZ.
[23]	XP	Configure extended page table configuration. This bit configures the hardware page translation mechanism: 0 = subpage AP bits enabled 1 = subpage AP bits disabled.
[22]	U	This bit enables unaligned data access operation, including support for mixed little-endian and big-endian data.[1]
[21:16]	-	Writing to these bits has no effect. Read as 6'b000101.
[15]	L4	Configure if load instructions to PC set T bit: 0 = loads to PC set the T bit 1 = loads to PC do not set the T bit (ARMv4 behavior). For more details see the ARM Architecture Reference Manual.
[14]	-	Reserved. SBO/RAO.
[13]	V	Location of exception vectors: 0 = normal exception vectors selected, address range = 0x00000000-0x0000001C 1 = high exception vectors selected, address range = 0xFFFF0000-0xFFFF001C.
[12]	I	Level one instruction cache enable/disable: 0 = instruction cache disabled 1 = instruction cache enabled.
[11]	Z	Program flow prediction: 0 = program flow prediction disabled 1 = program flow prediction enabled. Program flow prediction includes static and dynamic branch prediction and the return stack. This bit enables all three forms of program flow prediction. You can enable or disable each form individually by setting bits in the Auxiliary Control Register. See c1, Auxiliary Control Register.
[10]	-	Reserved. SBZ.
[9]	R	ROM protection. (Deprecated).
[8]	S	System protection. (Deprecated).
[7]	-	Reserved. SBZ.
[6:3]	-	Reserved. SBO.
[2]	C	Level one data cache enable/disable: 0 = data cache disabled 1 = data cache enabled.
[1]	A	Strict data address alignment fault enable/disable: 0 = strict alignment fault checking disabled 1 = strict alignment fault checking enabled. The A bit setting takes priority over the U bit. The Data Abort trap is taken if strict alignment is enabled and the data access is not aligned to the width of the accessed data item.
[0]	M	MMU enable/disable: 0 = MMU disabled 1 = MMU enabled. Take care with the address mapping of the code sequence used to enable the MMU, see Enabling the MMU. See Disabling the MMU for restrictions and effects of having caches enabled with the MMU disabled.
[1] This bit is affected by the setting of the A bit in this register.