MIPI Bridge Initial Code

最新推荐文章于 2024-02-26 00:43:30 发布

Phenixyf

最新推荐文章于 2024-02-26 00:43:30 发布

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本文链接：https://blog.csdn.net/phenixyf/article/details/38874345

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1. 向2828 写command/data

// SSD2828 Command Mode (LP) Initial 
void Initial_SSD2828_CMDMode(void)
{
	SPI_2828_WrCmd(0xb9);
	SPI_WriteData(0x00);//1=PLL disable
	SPI_WriteData(0x00);
	// Configure setting
	SPI_2828_WrCmd(0xb7);
	SPI_WriteData(0x00);	
	SPI_WriteData(0x00);   
	// VC setting
	SPI_2828_WrCmd(0xb8);	
	SPI_WriteData(0x00);	
	SPI_WriteData(0x00);   
	// PLL setting
	SPI_2828_WrCmd(0xBA);//PLL=(TX_CLK/MS)*NS 8228=480M 4428=240M  061E=120M 4214=240M 821E=360M 8219=300M
	SPI_WriteData(0x14);//D7-0=NS(0x01 : NS=1)
	SPI_WriteData(0x42);//D15-14=PLL范围 00=62.5-125 01=126-250 10=251-500 11=501-1000  DB12-8=MS(01:MS=1)
	// LP clk setting
	SPI_2828_WrCmd(0xBB);//LP Clock Divider LP clock = 400MHz / LPD / 8 = 240 / 8 / 4 = 7.5MHz
	SPI_WriteData(0x03);//D5-0=LPD=0x1 – Divide by 2
	SPI_WriteData(0x00);

	SPI_2828_WrCmd(0xb9);
	SPI_WriteData(0x01);//1=PLL enable
	SPI_WriteData(0x00);
	// Channel number setting
	SPI_2828_WrCmd(0xDE);//通道数
	SPI_WriteData(0x00);//11=4LANE 10=3LANE 01=2LANE 00=1LANE
	SPI_WriteData(0x00);

	TimerDelay(100);

}

2. 发送RGB信号前Initial (Video信号配置)

// SSD2828 Video Mode (HS) Initial
void Initial_SSD2828_VedioMode(void)
{
	// 配置RGB interface
	SPI_2828_WrCmd(0xB6);// RGB interface configure
	SPI_WriteData(0x03);
	SPI_WriteData(0x00);

	SPI_2828_WrReg(0xB1, 0x06FF  ); 	// H  V //HSA/VSA			//2
	SPI_2828_WrReg(0xB2, 0x0312  ); 	//H V  //HBP/VBP 
	SPI_2828_WrReg(0xB3, 0x080c  );  	//H V  //HFP/VFP 
	SPI_2828_WrReg(0xB4, 0x0438  );		 //1200	   	V  
	SPI_2828_WrReg(0xB5, 0x0780  ); 	 //1920		H

	SPI_2828_WrCmd(0xb9);
	SPI_WriteData(0x00);	//1=PLL disable
	SPI_WriteData(0x00);
	// VC setting
	SPI_2828_WrCmd(0xb8);	
	SPI_WriteData(0x00);
	SPI_WriteData(0x00);   //VC(Virtual ChannelID) Control Register
	// PLL setting
	SPI_2828_WrCmd(0xBA);//PLL=(TX_CLK/MS)*NS 8228=480M 4428=240M  061E=120M 4214=240M 821E=360M 8219=300M 8225=444M 8224=432
	SPI_WriteData(0x4b);//D7-0=NS(0x01 : NS=1)   //0X28
	SPI_WriteData(0xC2);//D15-14=PLL范围 00=62.5-125 01=126-250 10=251-500 11=501-1000  DB12-8=MS(01:MS=1) //0X82
	// LP clk setting
	SPI_2828_WrCmd(0xBB);//LP Clock Divider LP clock = 400MHz / LPD / 8 = 480 / 8/ 8 = 7.5MHz
	SPI_WriteData(0x07);//D5-0=LPD=0x1 – Divide by 2
	SPI_WriteData(0x00);

	SPI_2828_WrCmd(0xb9);
	SPI_WriteData(0x01);//1=PLL enable
	SPI_WriteData(0x00);
	// Channel number setting
	SPI_2828_WrCmd(0xDE);//通道数
	SPI_WriteData(0x03);//11=4LANE 10=3LANE 01=2LANE 00=1LANE
	SPI_WriteData(0x00);
	// Color order setting
	SPI_2828_WrCmd(0xD6);//  05=BGR  04=RGB
	SPI_WriteData(0x05);//D0=0=RGB 1:BGR D1=1=Most significant byte sent first
	SPI_WriteData(0x00);

	// Delay setting
	SPI_2828_WrCmd(0xc9);	// Delay setting
	SPI_WriteData(0x02);
	SPI_WriteData(0x23);   //p1: HS-Data-zero  p2: HS-Data- prepare  --> 8031 issue
	TimerDelay(5);

	SPI_2828_WrCmd(0xCA);	// Delay setting
	SPI_WriteData(0x01);//CLK Prepare
	SPI_WriteData(0x23);//Clk Zero

	SPI_2828_WrCmd(0xCB); //local_write_reg(addr=0xCB,data=0x0510)
	SPI_WriteData(0x10); //Clk Post
	SPI_WriteData(0x05); //Clk Per

	SPI_2828_WrCmd(0xCC); //local_write_reg(addr=0xCC,data=0x100A)
	SPI_WriteData(0x05); //HS Trail
	SPI_WriteData(0x10); //Clk Trail

	SPI_2828_WrCmd(0xD0); //local_write_reg(addr=0xCC,data=0x100A)
	SPI_WriteData(0x00); //HS Trail
	SPI_WriteData(0x00); //Clk Trail
	TimerDelay(5);
	// Configure setting
	SPI_2828_WrCmd(0xB7);
	SPI_WriteData(0x0B); 
	SPI_WriteData(0x02);TimerDelay(100);

}