介绍always @* (Verilog HDL)的意思
2011-03-08 19:44
Verilog-2001 adds a new wild card token, @*, which can
be used to represent a combinational logic sensitivity list.
The @* token indicates that the simulator or synthesis tool
should automatically be sensitive changes on any values
which are read in the following statement or statement
group. In the following example, the @* token will cause
the procedure to automatically be sensitive to changes on
sel, a or b.
always @* //combinationallogicsensitivity
if(sel)
y=a;
else
y=b;
// 回馈网友