`timescale 10ns / 10ns
module test (
CLK, RST
);
output CLK,RST;
reg CLK,RST;
initial
begin
CLK = 0;
RST = 0;
#10 RST <= 1;
#20 RST <= 0;
end
always
begin
#1 CLK <= ~CLK;
end
LFOutput testmine ( .clk(CLK), .rstin(RST), .data());
endmodule