Lattice Diamond中Verilog代码input导线unconnected解决方案

初学Verilog , 辛苦仿真了好久的代码, 等到准备烧写时,发现无法给input 定义的导线分配引脚.
自己折腾了1天,最后终于找到了原因 .

代码一定要像下面这样写.
/* synthesis syn_force_pads = 1 */
在引脚变量的上面加个定义. 告诉综合工具 , 不要把这个变量给优化掉了.

`timescale 10ns/1ps
 
 
module my_module(
	/* synthesis syn_force_pads = 1 */
	input wire clk, 
	/* synthesis syn_force_pads = 1 */
	input wire reset, 
	/* synthesis syn_force_pads = 1 */
	input [7:0] data_in 
	);
 
  // 内部变量
  reg [7:0] internal_data;
 
  // 使用内部变量来处理输入数据
  always @(posedge clk) begin
    if (reset)
      internal_data <= 8'b0;
    else
      internal_data <= data_in;
  end
 
  // 输出逻辑
  assign out_data = internal_data;
 
endmodule

如果还是不行, 试试新建工程. 把代码复制过去.

下面是官网搜到的一点相关内容,

How to set the behavior of unused pins in an FPGA design? These are some of the workarounds:-**

1. In RTL code, assign the following attributes to the unused input:

   /* synthesis syn_force_pads=1 syn_noprune = 1 */

The ‘syn_noprune’ will not allow Synplify Pro to optimize unconnected I/O buffers and will increase resource utilization. So, as per your design requirement, it may or may not be used.

2. Under Strategy1 make the following setting:

   MAP Design–> Command line options = -u
   This ensures that the Mapper does not remove the unused I/Os.

3. In spreadsheet view, make pull mode =NONE