2021-06-11

Quartus ii实验报告八（第三个实验）
1.实验目的：
下载Quartur ii软件和modlsim并进行联合仿真。
2.实验内容：
参今日头条老师发的视频及电子书，然后用quartus ii和modlsim进行联合仿真
3.实验原理：建立V文件，书写和运行代码，完成联合仿真操作。

4实验工具：
pc机和Quartur ii软件和modlsim软件。

5.实验截图：

6.实验代码：
module div (clk, reset, start, A, B, D, R, ok, err);
parameter n = 32;
parameter m = 16;

input clk, reset, start;
input [n-1 : 0 ] A, B;
output [n+m-1 : 0 ] D;
output [n-1 : 0 ] R;
output ok, err;

wire invalid, carry, load, run;

div_ct1 UCTL (clk, reset, start, invalid, carry, load, run, err, ok);
div_datapath UDATAPATH (clk, reset, A, B, load, run, invalid, carry,D,R);

endmodule

module div_ctl(clk, reset, start, invalid, carry, load, run, err, ok);
parameter n = 32;
parameter m = 16;
parameter STATE_INIT = 3’b001;
parameter STATE_RUN = 3’b010;
parameter STATE_FINISH = 3’b100;
input clk, reset, start, invalid, carry;
output load, run, err, ok;

reg[2:0] current_state, next_state;
reg [5:0] cnt;
reg load, run, err, ok;

always @(posedge clk or negedge reset)
begin

if(!reset) begin

current_ state <= STATE_ INIT;
cnt <= 0;

end else begin

current_ state <= next_state;

if(run) cnt <= cnt + 1’b1;

end

end

always @(posedge clk or negedge reset)
begin

if(!reset) begin

err <= 0;

end else if (next_state==STATE_RUN) begin
if(invalid) err <= 1;

end

end

always @(current_state or start or invalid or carry or cnt)
begin

load <= 1’b0;
ok <= 1’b0;
run <= 1’b0;

case (current_state)

STATE_INIT: begin

if(start) next_state <= STATE_RUN;
else next_state <= STATE_INIT;
load <= 1;

end

STATE_RUN : begin

run <= 1;

if(invalid) begin

next_state <= STATE_FINISH;
end else if(cnt==(n+m-1)) begin
next_state <= STATE_FINISH;
end else begin
next_state <= STATE_RUN;
end
STATE_FINISH : begin
ok <= 1;

next_state <= STATE_FINISH;
end

default : begin

next_state <= STATE_INIT;

end

endcase

end

endmodule

module div_datapath(clk, reset, A, B, load, run, invalid, carry, D, R);
parameter n = 32;
parameter m = 16;
input clk, reset;
input [n-1:0] A, B;
input load, run;
output invalid, carry;
output [n+m-1:0] D;
output [n-1:0] R;

reg [n+n+m-2:0] R0;
reg [n+m-1:0] D;
reg [n-1:0] B0;
reg carry;

wire invalid;
wire [n-1:0] DIFF, R;
wire CO

assign R = {carry, R0[n+n+m-2:n+m]};
assign invalid = (B0==0) ;
sub sub(R0[n+n+m-2:n+m-1], B0, 1’b0， DIFF, CO);
always @(posedge clk)
begin
if (load) begin
D<= 0;
R0 <= {{(n-1){1’b0}}, A, {m{1’b0}}};
B0 <= B;

carry <= 1’b0;

end

else if (run) begin

if(CO && !carry) begin

R0<={ R0, 1’b0 };

D <={ D[n+m-2:0],1’b0 );

carry <= R0[n+n+m-2];

end else begin

RO <= { DIFF, R0[n+m-2:0], 1’b0 );
D <={ D[n+m-2:0],1’b1 };

carry <= DIFF[n-1];

end

end

end
endmodule

7.软件下载网站：
1.复制这段内容后打开百度网盘App，操作更方便哦。 链接：https://pan.baidu.com/s/1ZT0ovNAAZ_j3jTGzVCYfbQ
提取码：5jf2