# 8位数码管显示频率计设计（FPGA）

always@(posedge clk)//产生1s信号clkkbegin if(clkk_count==32'd24_999_999) begin clkk <= ~clkk; clkk_count <= 0; end else begin clkk_count <= clkk_count+1'b1; endend
接下来做一个类似这样的程序100khz，10khz，1khz的输入 
always@(posedge clk)//100khz fin
begin
if(fin_count==32'd249)
begin
fin=~fin;
fin_count <= 0;
end
else
fin_count <= fin_count+1'b1;
end


always@(posedge clkk) //ftctrl
begin
cnt_en <= ~cnt_en;
end


always@(clkk,cnt_en,load)
begin
begin
rst_cnt <= 1;
end
else
begin
rst_cnt <= 0;
end
end


always@(posedge rst_cnt or posedge fin)//counter
begin
if(rst_cnt)
begin
counter <= 0;
end
else if(cnt_en)
begin
counter <= counter+1'b1;
end
end


always@(posedge load)
begin
count_reg <= counter;
end


顶层代码：
module pinglv(clk,hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7);
input clk;
output [6:0]hex0,hex1,hex2,hex3,hex4,hex5,hex6,hex7;
reg clkk,fin;
reg [31:0]clkk_count;
reg [31:0]fin_count;
reg [31:0]counter;
reg [31:0]count_reg;
always@(posedge clk)//产生1s信号clkk
begin
if(clkk_count==32'd24_999_999)
begin
clkk <= ~clkk;
clkk_count <= 0;
end
else
begin
clkk_count <= clkk_count+1'b1;
end
end
//always@(posedge clk)//1khz fin
//begin
//	if(fin_count==32'd25_000)
//	begin
//		fin=~fin;
//		fin_count <= 0;
//	end
//	else
//		fin_count <= fin_count+1'b1;
//end
//always@(posedge clk)//10khz fin
//begin
//	if(fin_count==32'd2_499)
//	begin
//		fin=~fin;
//		fin_count <= 0;
//	end
//	else
//		fin_count <= fin_count+1'b1;
//end
always@(posedge clk)//100khz fin
begin
if(fin_count==32'd249)
begin
fin=~fin;
fin_count <= 0;
end
else
fin_count <= fin_count+1'b1;
end
always@(posedge clkk) //ftctrl
begin
cnt_en <= ~cnt_en;
end
begin
begin
rst_cnt <= 1;
end
else
begin
rst_cnt <= 0;
end
end
always@(posedge rst_cnt or posedge fin)//counter
begin
if(rst_cnt)
begin
counter <= 0;
end
else if(cnt_en)
begin
counter <= counter+1'b1;
end
end
begin
count_reg <= counter;
end
hex u0(count_reg[3:0],hex0);
hex u1(count_reg[7:4],hex1);
hex u2(count_reg[11:8],hex2);
hex u3(count_reg[15:12],hex3);
hex u4(count_reg[19:16],hex4);
hex u5(count_reg[23:20],hex5);
hex u6(count_reg[27:24],hex6);
hex u7(count_reg[31:28],hex7);
endmodule

module hex(A,LED7S);
input[3:0]A;
output[6:0]LED7S;
reg[6:0]LED7S;
always @(A)
begin
case(A)
4'd0:LED7S=7'b1000000;
4'd1:LED7S=7'b1111001;
4'd2:LED7S=7'b0100100;
4'd3:LED7S=7'b0110000;
4'd4:LED7S=7'b0011001;
4'd5:LED7S=7'b0010010;
4'd6:LED7S=7'b0000010;
4'd7:LED7S=7'b1111000;
4'd8:LED7S=7'b0000000;
4'd9:LED7S=7'b0010000;
4'd10:LED7S=7'b0001000;
4'd11:LED7S=7'b0000011;
4'd12:LED7S=7'b1000110;
4'd13:LED7S=7'b0100001;
4'd14:LED7S=7'b0000110;
4'd15:LED7S=7'b0001110;
default:LED7S=7'b1000000;
endcase
end
endmodule


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