FPGA Verilog的单精度浮点型小数处理方法

1、操作数预处理
begin
rA <= { A[31], A[30:23], 1’b1, A[22:0] };
rB <= { B[31], B[30:23], 1’b1, B[22:0] };
end

2、运算
begin
isSign <= A[31] ^ B[31];
BDiff = rB[31:24] - 8’d127;
rExp <= rA[31:24] - BDiff;
Temp <= { rA[23:0] , 24’d0} / { 24’d0 , rB[23:0] };
end

3、结果调整
begin
if( Temp[25] == 1’b1 ) begin Temp <= Temp << 22; end
else if( Temp[24] == 1’b1 ) begin Temp <= Temp << 23; end
else if( Temp[23] == 1’b1 ) begin Temp <= Temp << 24; rExp <= rExp - 1’b1; end
end

4、输出和格式化
begin
if( rExp[9:8] == 2’b01 ) begin isOver <= 1’b1; rResult <= {1’b0,8’d127, 23’d0}; end
else if( rExp[9:8] == 2’b11 ) begin isUnder <= 1’b1; rResult <= {1’b0, 8’d127, 23’d0}; end
else if( Temp[47:24] == 24’d0 ) begin isZero <= 1’b1; rResult <= {1’b0, 8’d127, 23’d0}; end
else rResult <= { isSign, rExp[7:0], Temp[46:24] };
end