检测一个信号的上升沿以及下降沿

module posedge_in(clk,rst_n,data,data_edge,mode);
input clk, rst_n, data;
input[1:0]mode;
output data_edge;
reg en;
assign data_edge=rst_n==0?0:clk&en; 

always@(posedge data)begin
	en<=1'b1;
end
always@(negedge clk)begin
	en<=1'b0;
end
endmodule 
*******/


module Edge_Detect(input clk,input rst_n,input data,output pos_edge);    

reg [1:0]   data_r;
always @(posedge clk or negedge rst_n)begin   
if(rst_n == 1'b0)begin       
data_r <= 2'b00;   
end   
else begin       
data_r <= {data_r[0], data};   end
end 
assign  pos_edge = ~data_r[1] & data_r[0];
assign  neg_edge = data_r[1] & ~data_r[0];
assign  data_edge = pos_edge | neg_edge; 
endmodule