检测101序列的状态机以及代码

s_idle 代表初始状态
s1 代表出现第一个1
s2 代表出现第一个10
s3 代表出现了101

module test101(clk, rst_n, data,flag_101);
input clk, rst_n, data;
output reg flag_101;
reg [1:0] current_state;
reg [1:0] next_state;
parameter s_idle = 2'd0;
parameter s_1 = 2'd1;
parameter s_2 = 2'd2;
parameter s_3 = 2'd3;
always@(posedge clk)begin
 if(rst_n==0)begin
  current_state<=s_idle;
 end
 else begin
  current_state<=next_state;
 end
end
always@(*)begin
 case(current_state)
 s_idle:
  begin
   if(data) next_state = s_1;
   else next_state = s_idle;
  end
 s_1:
  begin
   if(data) next_state = s_1;
   else next_state = s_2;
  end
 s_2:
  begin
   if(data) next_state = s_3;
   else next_state = s_idle;
  end
 s_3:
  begin
   if(data) next_state = s_1;
   else next_state = s_2;
  end
 endcase

end
always@(posedge clk)begin
 if(rst_n==0)begin
  flag_101<=1'b0;
 end
 else begin
  case(next_state)
 s_idle:
  begin
   flag_101<=1'b0;
  end
 s_1:
  begin
   flag_101<=1'b0;
  end
 s_2:
  begin
   flag_101<=1'b0;
  end
 s_3:
  begin
   flag_101<=1'b1;
  end
  endcase
 end
 
end
endmodule