FPGA二四八分频
```java
module ledrgb(clk,ledr,ledg,ledb);
input clk;
output reg ledr=1'b0;
output reg ledg=1'b0;
output reg ledb=1'b0;
always@(posedge clk) 二分频
begin
ledr=~ledr;
end
always@(posedge ledr) 四分频
begin
ledg=~ledg;
end
always@(posedg..
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2021-11-20 11:54:59 ·
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