```java
module ledrgb(clk,ledr,ledg,ledb);
input clk;
output reg ledr=1'b0;
output reg ledg=1'b0;
output reg ledb=1'b0;
always@(posedge clk) 二分频
begin
ledr=~ledr;
end
always@(posedge ledr) 四分频
begin
ledg=~ledg;
end
always@(posedge ledg) 八分频
begin
ledb=~ledb;
end
endmodule
/***************/
`timescale 1ns/1ns
module ledrgbtop(); //可以不带括号
reg sysclk;
wire ledr;
wire ledg;
wire ledb;
initial
begin
sysclk=0;
forever #20 sysclk=~sysclk;
end
ledrgb u1(
.clk(sysclk),
.ledr(ledr),
.ledg(ledg),
.ledb(ledb)
); //芯片编号
endmodule
FPGA二四八分频
最新推荐文章于 2023-01-02 11:16:55 发布