第五十四讲设备树实现RGB驱动

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最新推荐文章于 2024-01-11 19:51:14 发布

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第五十四讲设备树实现RGB驱动

文章目录

第五十四讲设备树实现RGB驱动

一、基础知识

1、GPIO Write Mode

以下摘抄自官方数据手册（用户手册），前面提到过。

The programming sequence for driving output signals should be as follows:
1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need to read loopback pad value through PSR
2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
3. Write value to data register (GPIO_DR).

// SET PADS TO GPIO MODE VIA IOMUX.
write sw_mux_ctl_pad_<output[0-3]>.mux_mode, <GPIO_MUX_MODE>
// Enable loopback so we can capture pad value into PSR in output mode
write sw_mux_ctl_pad_<output[0-3]>.sion, 1
// SET GDIR=1 TO OUTPUT BITS.
write GDIR[31:4,output3_bit,output2_bit, output1_bit, output0_bit,] 32'hxxxxxxxF
// WRITE OUTPUT VALUE=4’b0101 TO DR.
write DR, 32'hxxxxxxx5
// READ OUTPUT VALUE FROM PSR ONLY.
read_cmp PSR, 32'hxxxxxxx5

2、硬件连接

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颜色	引脚
RGB_R	GPIO1_IO04
RGB_B	CSI_VSYNC
RGB_G	CSI_HSYNC

3、重要寄存器（参考IMXULL用户手册）

RGB_R

寄存器	作用	地址
CCM_CCGR1	The figure below represents the CCM Clock Gating Register 1(CCM_CCGR1). The clock gating registers define the clock gating for power reduction of each clock (CG(i) bits). There are 8 CGR registers. The number of registers required is determined by the number of peripherals in the system.	0x20c406c
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04	设置引脚功能	0x20e006c
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04	设置引脚属性	0x20e02f8
GPIOx_DR	The 32-bit GPIO_DR register stores data that is ready to be driven to the output lines. If the IOMUXC is in GPIO mode and a given GPIO direction bit is set, then the corresponding DR bit is driven to the output. If a given GPIO direction bit is cleared, then a read of GPIO_DR reflects the value of the corresponding signal.Two wait states are required in read access for synchronization.	0x209c000
GPIOx_GDIR	GPIO_GDIR functions as direction control when the IOMUXC is in GPIO mode. Each bit specifies the direction of a one-bit signal. The mapping of each DIR bit to a corresponding SoC signal is determined by the SoC’s pin assignment and the IOMUX table. For more details consult the IOMUXC chapter.	0x209c004

RGB_G(GPIO4_IO20)

寄存器	作用	地址
CCM_CCGR3	时钟使能	20C_4074h
IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC	引脚功能	20E_01E0
IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC	引脚属性	20E_046C
GPIOx_DR	输出控制	20A_8000
GPIOx_GDIR	输入输出控制	20A_8004