基于fpga的多功能数字钟（未完成）

最新推荐文章于 2024-06-26 17:10:45 发布

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最新推荐文章于 2024-06-26 17:10:45 发布

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本文链接：https://blog.csdn.net/qq_36310902/article/details/85108051

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参考链接

https://wenku.baidu.com/view/c3bb628d85254b35eefdc8d376eeaeaad0f31640.html

实现功能

分频

模60计数器

计时、校分、校秒

报时

比较器

闹钟

模块控制

七段数码管译码

显示电路

显示学号

约束代码

分频

//从100mhz分成1hz和2hz的脉冲信号，另外留一个1khz做备用
module fdiv(
clk,_1HZ,_2HZ,_1kHZ
           );
 input clk;
 output _1HZ,_2HZ,_1kHZ;
 reg _1HZ=0,_2HZ=0,_1kHZ=0;
 reg [24:0] cnt1=0,cnt2=0,cnt3=0;
 
  always @(posedge clk)//1HZ
  begin
 if(cnt1<25'd49999999)
    cnt1<=cnt1+1;
 else
    begin
        _1HZ<=~_1HZ;
      cnt1=0;
    end
end    

 always @(posedge clk)//2KHZ
 begin
if(cnt3<25'd24999999)
   cnt2<=cnt2+1;
else
   begin
       _2HZ<=~_2HZ;
     cnt2=0;
   end
end    
 always @(posedge clk)//1KHZ频率
  begin
 if(cnt3<25'd49999)
    cnt3<=cnt3+1;
 else
    begin
        _1kHZ<=~_1kHZ;
      cnt3=0;
    end
end    
endmodule

模60计数器

module countM60(
    cntMH,cntML,nCR,,_1HZ    //分位高位，分位低位，nCR是清零信号,来一个0就清零，EN是使能端，CP是时钟信号,来一个上边缘就加一,
    );
  input _1HZ,nCR;
  output[3:0]  cntMH,cntML;
  reg [3:0]  cntMH=0,cntML=0;

always @(posedge _1HZ or negedge nCR )//时钟端上升沿，ncr清零信号下降沿清零
begin
 if(~nCR)//清零信号为0
        {cntMH,cntML}<=8'b00;//置零
  //else if(EN)//使能端不为1
    //  {cntMH,cntML}<={cntMH,cntML};//暂停
        else if(cntML>9||cntMH>5||cntMH==5&&cntML==9)//分低位大于9或分高位高于5或即为5又为9
        begin
        {cntMH,cntML}<=8'b00;//置零
        end
    else if(cntMH<5&&cntML==9)//分高位小于5分低位等于9
        begin
        cntMH<=cntML+1'b1;//分高位加一
        cntML<=4'b0;//分低位置零
        end
    else
        cntML<=cntML+1'b1;//分低位进位
    end   

endmodule

计时、校分、校秒

module top_clock(
 Minute,Second,_1HZ,_2HZ,nCR,Adjmin,Adjsec,Conmin
    );
    input _1HZ,_2HZ,nCR,Adjmin,Adjsec,Conmin;
    output [7:0] Minute,Second;
    
    wire  [7:0] Minute,Second;
  //  supply1 Vdd;//设定使能
    reg Seccp;//秒激励信号
    reg Conmin;
    wire Mincp;//分激励信号
    //module countM60(
    //    cntMH,cntML,nCR,EN,CP    //分位高位，分位低位，nCR是清零信号,来一个0就清零，EN是使能端，CP是时钟信号,来一个上边缘就加一,
    //    );
//    always @(posedge _1HZ or negedge nCR )
    countM60 U1(Second[7:4],Second[3:0],nCR,~Seccp);
    countM60 U2(Minute[7:4],Minute[3:0],nCR,~Mincp);
    
    always 
    if(Conmin)
       begin
         if(~Adjsec)
         begin
         Seccp=_1HZ;
         end
    else
        begin
        Seccp=_2HZ;
        end
    end
    //assign Seccp =Adjsec?_2HZ:(Second==4'd59);
    assign Mincp =Adjmin?_2HZ:(Second==4'd59);//分钟激励如调分，则按2hz，否则由59时进位
    
    
    
endmodule

报时

module radio(
ALARM,Minute,Secend,_1kHZ
    );
    input _1kHZ;
    input [7:0] Minute ,Second;
    output ALARM;//报时输出
    
    reg ALARM;
    
    always @( Minute or Second)
    if (Minute == 4'd59)
    case(Second)
    4'd53:ALARM = _1kHZ;
    4'd55:ALARM = _1kHZ;
    4'd57:ALARM = _1kHZ;
    4'd59:ALARM = _1kHZ;
    default:ALARM=1'b0;
    endcase
    else ALARM =1'b0;
        
    
endmodule

比较器

module comparator(
    EQU,A,B
    );
    input [3:0] A,B;
    output EQU;
    assign EQU=(A==B);
endmodule

闹钟

module ring(
ALARM_clock,setmin,setsec,Minute,Second,Setminkey,Setseckey,_1kHZ,_1HZ,_2HZ,Conring
    );//闹钟输出，设定分，设定秒，分输入，秒输入，分校正，秒校正，频率，闹钟按钮
    output ALARM_clock;
    output [7:0] setmin,setsec;
    
    reg Seccp;
    
    wire  ALARM_clock;
    wire [7:0] setmin,setsec;
    input _1kHZ,_2HZ,_1HZ;
    input [7:0] Minute,Second;
    input Setminkey,Setseckey,Conring;
    
 //   supply1 Vdd;
    
    wire minH,minL,secH,secL;//比较之后的输出是否为1
    wire time_EQU;
    
    always 
        if(Conring)
           begin
             if(~Setseckey)
             begin
             Seccp=_1HZ;
             end
        else
            begin
            Seccp=_2HZ;
            end
        end
    
    countM60 SU1(setmin[7:4],setmin[3:0],Setminkey,Seccp);
    countM60 SU2(setsec[7:4],setsec[3:0],Setseckey,Seccp);
    /*
    module countM60(
        cntMH,cntML,nCR,EN,CP    //分位高位，分位低位，nCR是清零信号，EN是使能端，CP是时钟信号,来一个上边缘就加一,
        );
    */
    //调用比较器
    comparator SU4 (minH,setmin[7:4],Minute[7:4]);
    comparator SU5 (minL,setmin[3:0],Minute[3:0]);
    comparator SU6 (secH,setsec[7:4],Second[7:4]);
    comparator SU7 (secL,setsec[3:0],Second[3:0]);
    
    assign time_EQU=(minH&&minL&&secH&&secL);                                       //四个都是1才行
    
    
    assign ALARM_clock=(time_EQU);
   //assign ALARM_clock=Ctring?(time_EQU):1'b0;
   // alarm_clock=ctring?(time_equ)&&(((second[0]==1'b1)&&_500hz)||((second[0]==1'b0)&&_1khz))):1'b0
    //上面是连蜂鸣器的代码，在奇偶时候分别以500hz，1000响，产生闹钟效果
endmodule

模块控制

//模式选择  0正常计时  1闹钟定时
module mode(
    mode,Minute,Second,setmin,setsec,LED_Min,LED_Sec,ALARM,ALARM_clock,ALARMout
    );
    input  mode,ALARM,ALARM_clock;
    input [7:0] Minute,Second,setmin,setsec;
    
    output [7:0] LED_Min,LED_Sec;
    output ALARMout;
    
    wire ALARM,ALARM_clock;
    wire [7:0] setmin,setsec;
    
    assign ALARMout=ALARM||ALARM_clock;//alarn输出在报时和闹钟均有效
    assign LED_Min=mode?setmin:Minute;
    assign LED_Sec=mode?setsec:Second;
    
    
endmodule

七段数码管译码

module translate(
    Seg_in,Seg_outH,Seg_outL
    );
    input [7:0] Seg_in;//输入的数码
    output [7:0] Seg_outH;//翻译高位
    output [7:0] Seg_outL;//翻译低位
    
    wire [7:0] Seg_outH,Seg_outL;
    reg [7:0]Seg_outH1,Seg_outL1;
    
    always @(Seg_in[7:4])
    case (Seg_in[7:4])
    4'b0000 : Seg_outH1=8'b11000000;//0
    4'b0001 : Seg_outH1=8'b11111001;//1
    4'b0010 : Seg_outH1=8'b10100100;//2
    4'b0011 : Seg_outH1=8'b10110000;//3
    4'b0100 : Seg_outH1=8'b10011001;//4
    4'b0101 : Seg_outH1=8'b10010010;//5
    4'b0110 : Seg_outH1=8'b10000010;//6
    4'b0111 : Seg_outH1=8'b11111000;//7
    4'b1000 : Seg_outH1=8'b10000000;//8
    4'b1001 : Seg_outH1=8'b10010000;//9
    default : Seg_outH1=8'b10100011;//error
    endcase
    
    always @(Seg_in[3:0])
    case (Seg_in[3:0])
    4'b0000 : Seg_outL1=8'b11000000;//0
    4'b0001 : Seg_outL1=8'b11111001;//1
    4'b0010 : Seg_outL1=8'b10100100;//2
    4'b0011 : Seg_outL1=8'b10110000;//3
    4'b0100 : Seg_outL1=8'b10011001;//4
    4'b0101 : Seg_outL1=8'b10010010;//5
    4'b0110 : Seg_outL1=8'b10000010;//6
    4'b0111 : Seg_outL1=8'b11111000;//7
    4'b1000 : Seg_outL1=8'b10000000;//8
    4'b1001 : Seg_outL1=8'b10010000;//9
    default : Seg_outL1=8'b10100011;//error
    endcase   
    
    assign Seg_outH=Seg_outH1;
    assign Seg_outL=Seg_outL1;

endmodule

显示电路（有错，主要是LED_min/sec那里，你可以看一下）

module trans(
_1kHZ,LED_Min,LED_Sec,LED,SELE
    );
    
    input [7:0] LED_Min;
    input [7:0] LED_Sec;
    input _1kHZ;
    output [7:0] LED;
    output [3:0] SELE; 
    
    wire [7:0]  SGML,SGMH,SGSL,SGSH;//分低高，秒低高
    reg [1:0] count=2'b00;
    wire [3:0] SELE;
    wire [7:0] LED;
    reg  [7:0] SG;
    reg  [3:0] SEL=1110;
    
    translate ST1 (LED_Min,SFMH,SGML);
    translate ST2 (LED_Sec,SFSH,SGSL);
    
    always @(posedge _1kHZ)
    case (count)
    2'b00:
            begin
            SG=SGSL;
            SEL=4'b1110;
            count = count +1'b1;
            end
    2'b01:
            begin
            SG=SGSH;
            SEL=4'b1101;
            count = count +1'b1;
            end
    2'b10:
            begin
            SG=SGML[7:0]+8'b10000000;
            SEL=4'b1011;
            count = count +1'b1;
            end
    2'b11:
            begin
            SG=SGMH;
            SEL=4'b0111;
            count = count +1'b1;
            end                                              
   endcase

   assign SELE=~SEL;//挑选哪一个数字晶体管
   assign LED=~SG;//输出信号
     
endmodule

显示学号

    module number(clk,LED,an);
    input clk;
    output reg [3:0] an;//前四个
    output reg [7:0] LED;//八位
    
    reg [19:0] count;//计数
    reg [1:0] a;//四选一
    reg clk_1k;
    
    initial//置初值
    begin
    an<=4'b0001;
    clk_1k<=0;
    a<=0;
    end
    
    always @ (posedge clk)
      if (count<49999)
         count<=count+1;
       else
       begin
          count<=0;
          clk_1k=~clk_1k;
       end
    
    
    always @(posedge clk_1k)
    begin
    case(a)
    0:
    begin
    an<=4'b0001;
    LED<=8'b1000_0110;//1
    end
    
    1:
    begin
    an<=4'b0010;
    LED<=8'b0110_1101;//5
    end
    
    2:
    begin
    an<=4'b0100;
    LED<=8'b0000_0110;//1
    end
    
    default:
    begin
    an<=4'b1000;
    LED <= 8'b0011_1111;//0
    end
    
    endcase
    a<=a+1;
    end
    endmodule

约束代码

set_property PACKAGE_PIN P17 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]


#左半部分
set_property PACKAGE_PIN G2 [get_ports an[3]]
set_property IOSTANDARD LVCMOS33 [get_ports an[3]]
set_property PACKAGE_PIN C2 [get_ports an[2]]
set_property IOSTANDARD LVCMOS33 [get_ports an[2]]
set_property PACKAGE_PIN C1 [get_ports an[1]]
set_property IOSTANDARD LVCMOS33 [get_ports an[1]]
set_property PACKAGE_PIN H1 [get_ports an[0]]
set_property IOSTANDARD LVCMOS33 [get_ports an[0]]

set_property PACKAGE_PIN D5 [get_ports LED[7]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[7]]
set_property PACKAGE_PIN B2 [get_ports LED[6]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[6]]
set_property PACKAGE_PIN B3 [get_ports LED[5]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[5]]
set_property PACKAGE_PIN A1 [get_ports LED[4]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[4]]
set_property PACKAGE_PIN B1 [get_ports LED[3]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[3]]
set_property PACKAGE_PIN A3 [get_ports LEDl[2]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[2]]
set_property PACKAGE_PIN A4 [get_ports LED[1]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[1]]
set_property PACKAGE_PIN B4 [get_ports LED[0]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[0]]

#校分按钮
set_property PACKAGE_PIN R11 [get_ports Adjmin]
set_property IOSTANDARD LVCMOS33 [get_ports Adjmin]]
#校秒按钮
set_property PACKAGE_PIN V1 [get_ports Adjmin]
set_property IOSTANDARD LVCMOS33 [get_ports Adjmin]]
#清零按钮
set_property PACKAGE_PIN R1 [get_ports nCR]
set_property IOSTANDARD LVCMOS33 [get_ports nCR]]
#模式扳
set_property PACKAGE_PIN R15 [get_ports mode]
set_property IOSTANDARD LVCMOS33 [get_ports mode]]
#校分设置开关
set_property PACKAGE_PIN N4 [get_ports Conmin]
set_property IOSTANDARD LVCMOS33 [get_ports Conmin]]
#闹钟设置开关
set_property PACKAGE_PIN M4 [get_ports Conring]
set_property IOSTANDARD LVCMOS33 [get_ports Conring]]




#右半部分
set_property PACKAGE_PIN G1 [get_ports SELE[3]]
set_property IOSTANDARD LVCMOS33 [get_ports SELE[3]]
set_property PACKAGE_PIN F1 [get_ports SELE[2]]
set_property IOSTANDARD LVCMOS33 [get_ports SELE[2]]
set_property PACKAGE_PIN E1 [get_ports SELE[1]]
set_property IOSTANDARD LVCMOS33 [get_ports SELE[1]]
set_property PACKAGE_PIN G6 [get_ports SELE[0]]
set_property IOSTANDARD LVCMOS33 [get_ports SELE[0]]



set_property PACKAGE_PIN H2 [get_ports LED[7]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[7]]
set_property PACKAGE_PIN D2 [get_ports LED[6]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[6]]
set_property PACKAGE_PIN E2 [get_ports LED[5]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[5]]
set_property PACKAGE_PIN F3 [get_ports LED[4]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[4]]
set_property PACKAGE_PIN F4 [get_ports LED[3]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[3]]
set_property PACKAGE_PIN D3 [get_ports LEDl[2]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[2]]
set_property PACKAGE_PIN E3 [get_ports LED[1]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[1]]
set_property PACKAGE_PIN D4 [get_ports LED[0]]
set_property IOSTANDARD LVCMOS33 [get_ports LED[0]]

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基于fpga的多功能数字钟（未完成）

参考链接https://wenku.baidu.com/view/c3bb628d85254b35eefdc8d376eeaeaad0f31640.html实现功能分频模60计数器计时、校分、校秒报时比较器闹钟模块控制七段数码管译码显示电路显示学号约束代码分频//从100mhz分成1hz和2hz的脉冲信号，另外留一个1khz...
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