Conceptions of Linux Operating System

Control Registers

• CR0: contains the system control flags that are used to control the operation mode and state of the processor, these flags are as follows:
  – PE, bit 0, Protection Enable flag. When PE=1, the processor will work under protection mode, and when PE=0, the real-address mode is enabled. This flag only opens segment-level protection, and do not enable paging directly. To enable paging, both PE and PG flags must be set.
  – PG, bit 31, Paging flag. When PG=0, the paging mechanism is disabled, and in this case, all the linear address is equal to physical address. However, if one wants to enable paging mechanism, both PG and PE flags must be set, that is, PG=1 and PE=1. The combination PG=1 and PE=0 is invalid, and a general protection exception will be thrown by the processor.
  – TS, bit 3, Task Switched flag, …
  – …

• CR1: reserved.

• CR2: is used to save the linear address that caused a page-fault exception.
  – “The processor loads the CR2 register with the 32-bit linear address that generated the exception. The page-fault handler can use this address to locate the corresponding page directory and page-table entries. Another page fault can potentially occur during execution of the page-fault handler; the handler should save the contents of the CR2 register before a second page fault can occur.”
  – “Processors update CR2 whenever a page fault is detected. If a second page fault occurs while an earlier page fault is being delivered, the faulting linear address of the second fault will overwrite the contents of CR2 (replacing the previous address). These updates to CR2 occur even if the page fault results in a double fault or occurs during the delivery of a double fault.”

• CR3, also called as PDBR(Page-Directory Base address Register), bit 12 – bit 31 are used to save the address and bit 0 – bit 11 are reserved.

Page Table

• A table that is resident in physical memory.
• A page table is associated to a process.
• The size of each item in page table is 32 bits.
• Each item of page table stored a base physical address of a page.
• The base physical address information stored in a page table item only occupies 20 bits due to the size of a page is 4K and each page is 4K-aligned in physical memory.
• The high 20 bits of a page table item are used to store the base physical address of a page, and the remaining 12 bits are used to store property informations of a page.
• A page table can be simply seemed as an array contains 2²⁰ physical address.
• Page table is used to convert a linear address(also 32-bit size) to a physical address, and the high 20 bits in linear address are used to look up the 2²⁰ physical address page table and the remaining low 12 bits are the offset of the acquired 4K-size page.
• Each page table contains 2²⁰(1 M) page table items, and each item is of 32 bits(4B), that is, the total size of a page table can reach 4 MB.

Page Directory

• Page directory appears at the application of the two-level or multiple-level page table structures.
• For the two-level page table structures, the high 10 bits of the linear address are used to look up the first level table(also known as page directory), and the intermediate 10 bits are used to look up the second level table(called as page table).
• The first level table is called as page directory, and is stored in a 4K-size page, and is of 2¹⁰(1 K) 32-bit-length(4 B) items.
• The second level table is called as page table, and is stored in a 4K-size page, and is of 2¹⁰(1 K) 32-bit-length(4 B) items.
• Each page directory item points to a second-level table, because of the 2nd-lv table is also stored in a 4K-size page, the high 20 bits are used to search the corresponding page table, and the remaining 12 bits are used to store property informations like page table item.
• Each item in the second level table is the same as the page table item.
• Using page directory can enable the operating system to store the page table items just used by a procedure, saving the limited physical memory.
• CR3 register, also known as PDBR(Page Directory Base address Register), stores the base physical address of the page directory.

Paging Mechanism

• Paging mechanism is used to convert a linear address to a physical address. In the case of 32-bit processor and two-level paging mechanism, the 32-bit-size linear address is divided into three parts:
• the first ten bits for page directory, as the offset to find 1 in 1024 items, which indicates the location of the second page table;
• the middle ten bits for the second level table, as the offset to find 1 in 1024 items, which indicates the location of the 4K-size page frame;
• the last twelve bits for page frame, as the offset to find one byte in 4096 bytes, which indicates the data to be addressed.

Segment

• Segment is the base conception about the convertion mechanism from virtual address to linear address.
• Segment Base Address: indicates the beginning address of the segment in linear address space.
• Segment Limit: indicates the maximum available offset of the segment in virtual address space. As the size of a segment is variable, the Segment Limit defines the size of the segment.
• Segment Attributes: indicates the attributes of a segment, such as readable, writable, executable and privilege level and …

Segment Selector

• A segment selector is a 16-bit identifier of a segment, which points to a segment descriptor in GDT(Global Descriptor Table) or LDT(Local Descriptor Table). There are three fields in a segment selector:
• RPL(Requested Privilege Level), 2 bits(bit 0 and bit 1),
• TI(Table Index), bit 2, TI=0 indicates the descriptor is in GDT and TI=1 indicates the descriptor is in LDT.
• Index, the remaining 13 bits, bit 3 – bit 15, the offset of the descriptor stored in descriptor table.
• Inorder to efficiency, six segment selector registers are provided by the processor, they are CS, SS, DS, ES, FS, GS, and naturally each of them is 16-bit size. And each of the segment selector registers is followed by a shadow register, which stores segment address, segment limit and access and control informations of the segment descriptor that the segment selector points to.

Segment Descriptor

• A segment descriptor is a data structure item in GDT, IDT or LDT, which is used to provide state informations about the position, size and access of a segment to processor.
• The size of a segment descriptor is 64 bits(DW0, DW1), and it contains three main fields: Segment Base Address, Segment Limit, Segment Attributes.
• Segment Limit Field, indicates the size of a segment, occupies 20 bits in the segment descriptor(bit 0 – bit 15 in DW0 and bit 16 – bit 19 in DW1). The unit of the 20-bit number is indicated by the flag bit G, which is also stored in the segment descriptor. If G=0, the uint is B, and the limit range is 1B ~ 1MB; if G=1, the uint is 4KB, and the limit range is 4KB ~ 4GB.
• Base Address Field, is defined in 4GB linear address space that indicates the beginning of the segment, and this field occupies 32 bits in the segment descriptor(bit 16 – bit 31 in DW0, bit 0 – bit 7 and bit 24 – bit 31 in DW1). The segment base address shoud be of 16-byte-aligned to make the program a perfect performance.
• TYPE Field, indicates the type of the segment or gate, the access type of the segment and the extending direction of the segment. This field occupies 4 bits in the segment descriptor(bit 8 – bit 11 in DW1). The interpretation of this field depends on the segment descriptor type flag S.
• Descriptor Type Flag Field, indicates a segment descriptor is system segment descriptor(S=0) or application(code or data) segment descriptor(S=1). This field occupies 1 bit in the segment descriptor(bit 12).
• Descriptor Privilege Level Field, indicates the privilege level of the segment descriptor with a range from 0(hign level) to 3(low level). This field occupies 2 bits in the segment descriptor(bit 13 and bit 14). DPL is used to control the access of a segment.
• Segment Present Flag Field, indicates the segment is in memory(P=1) or not(P=0). This field occupies 1 bit in the segment descriptor(bit 15 in DW1). A segment-do-not-exist exception will occur when loads a segment selector of the segment descriptor into a segment registor in the case of P=0, and the memory manager software can use this flag bit to control the time that loading the segment into memory when really needed.
• D/B Flag Field, occupies 1 bit in the segment descriptor(bit 22 in DW1). For 32-bit code or data segments, this flag bit is always set to 1, and for 16-bit, clear to 0.
• Granularity Flag Field, indicates the uint of the segment limit field, occupies 1 bit in the segment descriptor(bit 23 in DW1). if G=0, the uint is byte, and if G=1, the uint is 4KB. When G=1 and the segment limit is 0, the effective offset of the segment is 0~4095.
• Available Bit, bit 20 in DW1, is available for system softwares.
• Reserved Bit, bit 21 in DW1, is reserved and should always set to 0.

References

• Intel® 64 and IA-32 Architectures Software Developer’s Manual