将缓存添加到配置文件
我们的目标是基于上次写好的simple.py配置文件构建一个更复杂的架构,如下图:
1 创建caches.py
详细步骤
在simple.py的configs/tutorial目录中创建一个新文件caches.py。第一步是导入要在此文件中扩展的SimObject。
from m5.objects import Cache
接下来,我们可以像对待任何其他Python类一样对待BaseCache对象并对其进行扩展。我们可以随意命名新的缓存。让我们从一级缓存开始。
class L1Cache(Cache):
assoc = 2
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
这里,我们设置BaseCache的一些没有默认值的参数。要查看所有可能的配置选项,并找出哪些是必需的,哪些是可选的,我们必须查看SimObject的源代码。
我们已经扩展BaseCache并设置了BaseCacheSimObject中大多数没有默认值的参数。接下来,让我们再介绍L1Cache的两个子类:L1DCache和L1ICache
class L1ICache(L1Cache):
size = '16kB'
class L1DCache(L1Cache):
size = '64kB'
我们继续创建一个带有合理参数的L2缓存。
class L2Cache(Cache):
size = '256kB'
assoc = 8
tag_latency = 20
data_latency = 20
response_latency = 20
mshrs = 20
tgts_per_mshr = 12
现在,我们已经指定了所需的所有必要参数 BaseCache,我们要做的就是实例化子类并将缓存连接到互连。但是,将许多对象连接到复杂的互连可以使配置文件快速增长并变得不可读。因此,首先让我们向的子类添加一些辅助函数。
在L1高速缓存中,我们添加两个功能,connectCPU将CPU连接到高速缓存并将connectBus高速缓存连接到总线。我们需要将以下代码添加到L1Cache该类中。
def connectCPU(self, cpu):
# need to define this in a base class!
raise NotImplementedError
def connectBus(self, bus):
self.mem_side = bus.slave
现在,我们的L1Cache类变为:
class L1Cache(Cache):
"""Simple L1 Cache with default values"""
# Default parameters for both L1 I and D caches
assoc = 2
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU-side port
This must be defined in a subclass"""
raise NotImplementedError
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
self.mem_side = bus.slave
接下来,我们必须connectCPU为指令和数据缓存定义一个单独的函数,因为I缓存和D缓存端口具有不同的名称。现在,我们的L1ICache和L1DCache类变为:
class L1ICache(L1Cache):
"""Simple L1 instruction cache with default values"""
# Set the default size
size = '16kB'
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU icache port"""
self.cpu_side = cpu.icache_port
class L1DCache(L1Cache):
"""Simple L1 data cache with default values"""
# Set the default size
size = '64kB'
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU dcache port"""
self.cpu_side = cpu.dcache_port
最后,让我们为L2Cache添加函数分别连接到内存侧和CPU侧总线。
def connectCPUSideBus(self, bus):
self.cpu_side = bus.master
def connectMemSideBus(self, bus):
self.mem_side = bus.slave
完整代码
caches.py的最终完整代码如下:
from m5.objects import Cache
class L1Cache(Cache):
assoc = 2
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
def connectCPU(self,cpu):
raise NotImplementedError
def connectBus(self,bus):
self.mem_side = bus.slave
class L1ICache(L1Cache):
size = '16kB'
def connectCPU(self,cpu):
self.cpu_side = cpu.icache_port
class L1DCache(L1Cache):
size = '64kB'
def connectCPU(self,cpu):
self.cpu_side = cpu.dcache_port
class L2Cache(Cache):
size = '256kB'
assoc