基于QuautusII的Verilog 数字时钟设计
(1)基本功能
①显示年、月、日、星期、时、分,秒,是否为闰年(只有校对生效情
况时间可以不连续) ;
②定时与闹铃:到设定的时间(选择周一至周末或具体日期)进行报警;
③校对:可手动调整年、月、日、星期、时、分。
(2)扩展功能
显示本周是一年中的第几周,以及是本学期中的第几周(设置开学日期
为第一周) 。
1.时钟调教及计时模块M,m_S;
reg [5:0] m_Mon,m_D;
reg [6:0] m_MS;
reg [15:0] m_Y;
assign H=m_H;
assign M=m_M;
assign S=m_S;
assign MS=m_MS;
assign Y=m_Y;
assign Mon=m_Mon;
assign D=m_D;
always @(posedge CLK)
if(~RSTn) //复位状态
begin
m_H<=8'b00000000;
m_M<=8'b00000000;
m_S<=8'b00000000;
m_MS<=8'b00000000;
m_Y<=16'h07e3;//16'h07e3;
m_Mon<=8'b00000001;
m_D<=8'b00000001;
end
else if(FLAG==3'b001) //001调时状态
begin
if(UP)
begin
m_H <= m_H + 1'b1;
if(m_H==8'd23)
m_H<=8'd0;
end
else if(DN)
begin
m_H<=m_H-1'b1;
if(m_H==8'd0)
m_H<=8'd23;
end
end
else if(FLAG==3'b010) //010调分状态
begin
if(UP)
begin
m_M<=m_M+1'b1;
if(m_M==8'd59)
m_M<=8'd0;
end
else if(DN)
begin
m_M<=m_M-1'b1;
if(m_M==8'd0)
m_M<=8'd59;
end
end
else if(FLAG==3'b011) //011调秒状态
begin
if(UP)
begin
m_S<=m_S+1'b1;
if(m_S==8'd59)
m_S<=8'd0;
end
else if(DN)
begin
m_S<=m_S-1'b1;
if(m_S==8'd0)
m_S<=8'd59;
end
end
else if(FLAG==3'b000)
begin
m_MS<=m_MS+1'b1; //000正常计时状态
if(m_MS==8'd100)
begin
m_MS<=8'd0;
m_S<=m_S+1'b1;
end
if(m_S==8'd60)
begin
m_S<=8'd0;
m_M<=m_M+8'd1;
end
if(m_M==8'd60)
begin
m_M<=8'd0;
m_H<=m_H+1'b1;
end
if(m_H==8'd24)
begin
m_H<=8'd0;
m_D<=m_D+1'b1;
end
if((m_Mon==8'd1)||(m_Mon==8'd3)||(m_Mon==8'd5)||(m_Mon==8'd7)||(m_Mon==8'd8)||(m_Mon==8'd10)||(m_Mon==8'd12))//big month
begin
if(m_D==8'd31)
begin
m_D<=8'd1;
m_Mon<=m_Mon+1'b1;
end
end
if((m_Mon==8'd4)||(m_Mon==8'd6)||(m_Mon==8'd9)||(m_Mon==8'd11))//small month
begin
if(m_D==8'd30)
begin
m_D<=8'd1;
m_Mon<=m_Mon+1'b1;
end
end