LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY key_scan is
port(clk:in std_logic;
rst:in std_logic;
key_col:out std_logic_vector(0 to 3);
key_row:in std_logic_vector(3 downto 0);
litarray:out std_logic_vector(7 downto 0);
litchar:out std_logic_vector(6 downto 0);
beep:out std_logic;
count_col:buffer integer range 0 to 3;
count_row:buffer integer range 0 to 3;
cap_col:buffer integer range 0 to 3;
cap_row:buffer integer range 0 to 3;
kout_1,kout_2,kout_3,kout_4:buffer std_logic;
kout:buffer std_logic);
end key_scan;
architecture key_scan_16 of key_scan is
component key_in_0
port (clk,kin:in std_logic;
kout:out std_logic);
end component;
component beep_16
port (clk,enbl: in std_logic;
freq_contl_1,freq_contl_2: integer range 1 to 4;
beep: out std_logic);
end component;
--signal count_col:integer range 0 to 3;
--signal count_row:integer range 0 to 3;
type col_matrix is array (1 to 4) of std_logic_vector(0 to 3);
signal col_detect:col_matrix;
signal c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,cA,cb,cC,cd,cE,cF: std_logic_vector(6 downto 0);
type char_4 is array (1 to 4) of std_logic_vector(6 downto 0);
type char_16 is array (1 to 4) of char_4;
signal disp_char: char_16;
begin
u1: key_in_0 port map (clk=>clk,kin=>key_row(0),kout=>kout_1 );
u2: key_in_0 port map (clk=>clk,kin=>key_row(1),kout=>kout_2 );
u3: key_in_0 port map (clk=>clk,kin=>key_row(2),kout=>kout_3 );
u4: key_in_0 port map (clk=>clk,kin=>key_row(3),kout=>kout_4 );
-- u5: beep_16 port map (clk=>clk,enbl=>kout,freq_contl_1=>cap_row,freq_contl_2=>cap_col,beep=>beep);
p1: process(rst,clk)
begin
col_detect<=("0111","1011","1101","1110");
if(rst='0') then count_col<=1;
elsif(clk'event and clk='1') then
if(count_col=5) then count_col<=1;
else
count_col<=count_col+1;
key_col<=col_detect(count_col);
case (key_row) is
when "0111" => cap_row<=0;cap_col<=count_col;beep<=clk;
when "1011" => cap_row<=1;cap_col<=count_col;beep<=clk;
when "1101" => cap_row<=2;cap_col<=count_col;beep<=clk;
when "1110" => cap_row<=3;cap_col<=count_col;beep<=clk;
when others => null;
end case;
end if;
end if;
end process;
p2:process(kout)
begin
kout<=kout_1 or kout_2 or kout_3 or kout_4;
disp_char(1)<=(c0,c1,c2,c3);
disp_char(2)<=(c4,c5,c6,c7);
disp_char(3)<=(c8,c9,cA,cb);
disp_char(4)<=(cC,cd,cE,cF);
c0<= "1111110";
c1<= "0110000";
c2<= "1101101";
c3<= "1111001";
c4<= "0110011";
c5<= "1011011";
c6<= "1011111";
c7<= "1110000";
c8<= "1111111";
c9<= "1111011";
cA<= "1110111";
cb<= "0011111";
cC<= "1001110";
cd<= "0111101";
cE<= "1001111";
cF<= "1000111";
if (kout='0') then
litchar<=disp_char(count_row)(count_col);
end if;
end process;
end;
key_in_0
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY key_in_0 IS
PORT(clk,kin:in std_logic;
kout:out std_logic);
END key_in_0;
ARCHITECTURE scan_key OF key_in_0 IS
SIGNAL a:std_logic;
SIGNAL count:integer range 0 to 9;
BEGIN
PROCESS(clk)
BEGIN
IF kin='1' THEN
count<=0;
ELSIF(clk' event and clk='1')
THEN
IF count=5 THEN count<=count;
ELSE count<=count+1;
END IF;
END IF;
IF count=4
THEN a<='0';
ELSE a<='1';
END IF;
END PROCESS;
kout<=a;
END scan_key;
```