基于FPGA的LED流水灯设计

1.首先分别建立建立两个模块div_clk和led_control。

div_clk模块：

module div_clk(clk,rst_n,clk_out);
input clk,rst_n;
output reg clk_out;

parameter DELAY =24'd999_999;
reg [23:0] cnt;
always @(posedge clk or negedge rst_n)
begin 
if(!rst_n)
cnt  <=24'd0;
else if (cnt==DELAY)
cnt <=24'd0;
else
cnt <=cnt+1'b1;
end
always@(posedge clk or negedge rst_n)
begin 
if(!rst_n)
clk_out <=1'd0;
else if(cnt ==DELAY)
  clk_out<=~clk_out;
end

endmodule

 

led_control模块：

module led_control(clk,rst_n,led_data);
input clk,rst_n;
output reg [7:0] led_data;
reg [2:0] current_state,next_state;
always@(posedge clk or negedge rst_n)
begin 
if(!rst_n)
current_state <=3'd0;
else 
current_st