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Sparse-YOLO: Hardware/Software Co-Design of an FPGA Accelerator for YOLOv2
Sparse-YOLO: Hardware/Software Co-Design of an FPGA Accelerator for YOLOv2ABSTRACT1 介绍2 背景2.1 YOLOv2算法2.2 ABM-SpConv算法3 系统设计3.1 目标异构平台3.2 HW/SW划分3.3 硬件结构设计3.3.1 DATA LOAD/STORE UNITS3.3.2 SPARSE CONVOLUTION UNIT3.3.3 ON-CHIP BUFFER DESIGN3.3.4 HARDWARE MAX原创 2021-04-27 16:20:32 · 722 阅读 · 1 评论 -
A Novel FPGA Accelerator Design for Real-Time and Ultra-Low Power Deep Convolutional Neural Networks
A Novel FPGA Accelerator Design for Real-Time and Ultra-Low Power Deep Convolutional Neural Networks Compared With Titan X GPUAbstart1.Introduction2.Background2.1 Related Work2.2 FPGA实现方法2.3 CNN_FPGA3.基于FPGA的CNN加速并行、流水线建模3.1 三维卷积运算的高速并行设计3.2 CNN加速的并行、流水线设计原创 2021-04-26 12:14:32 · 321 阅读 · 0 评论